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| 1995, 2000 data sheet 4-bit single-chip microcontroller description the m pd753108 is one of the 75xl series 4-bit single-chip microcontroller chips and has a data processing capability comparable to that of an 8-bit microcontroller. the existing 75x series containing an lcd controller/driver supplies an 80-pin package. the m pd753108 supplies a 64-pin package (12 12), which is suitable for small-scale systems. it features expanded cpu functions and can provide high-speed operation at a low supply voltage of 1.8 v compared with the existing m pd75308b. detailed function descriptions are provided in the following users manual. be sure to read it before designing. m pd753108 users manual: u10890e features ? low voltage operation: v dd = 1.8 to 5.5 v ? can be driven by two 1.5 v batteries ? internal memory ? program memory (rom): 4096 8 bits ( m pd753104) 6144 8 bits ( m pd753106) 8192 8 bits ( m pd753108) ? data memory (ram): 512 4 bits ? capable of high-speed operation and variable instruction execution time for power saving ? 0.95, 1.91, 3.81, 15.3 m s (@ 4.19 mhz with main system clock) ? 0.67, 1.33, 2.67, 10.7 m s (@ 6.0 mhz with main system clock) ? 122 m s (@ 32.768 khz with subsystem clock) ? internal programmable lcd controller/driver ? small package: 64-pin plastic lqfp (12 12), 64-pin plastic tqfp (12 12) ? one-time prom version: m pd75p3116 application remote controllers, cameras, hemadynamometers, electronic scale, gas meters, etc. unless otherwise indicated, references in this data sheet to the m pd753108 mean the m pd753104 and m pd753106. mos integrated circuit m pd753104, 753106, 753108 the mark shows major revised points. document no. u10086ej4v0ds00 (4th edition) date published september 2000 n cp(k) printed in japan the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information.
2 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 ordering information part number package m pd753104gc- -ab8 64-pin plastic qfp (14 14) m pd753104gk- -8a8 64-pin plastic lqfp (12 12) m pd753104gk- -9et 64-pin plastic tqfp (12 12) m pd753106gc- -ab8 64-pin plastic qfp (14 14) m pd753106gk- -8a8 64-pin plastic lqfp (12 12) m pd753106gk- -9et 64-pin plastic tqfp (12 12) m pd753108gc- -ab8 64-pin plastic qfp (14 14) m pd753108gk- -8a8 64-pin plastic lqfp (12 12) m pd753108gk- -9et 64-pin plastic tqfp (12 12) remark indicates rom code suffix. 3 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 overview of functions parameter function instruction execution time ? 0.95, 1.91, 3.81, 15.3 m s (@ 4.19 mhz with main system clock) ? 0.67, 1.33, 2.67, 10.7 m s (@ 6.0 mhz with main system clock) ? 122 m s (@ 32.768 khz with subsystem clock) internal memory rom 4096 8 bits ( m pd753104), 6144 8 bits ( m pd753106), 8192 8 bits ( m pd753108) ram 512 4 bits general-purpose register ? 4-bit operation: 8 4 banks ? 8-bit operation: 4 4 banks i/o port cmos input 8 on-chip pull-up resistors which can be specified by means of software: 7 cmos i/o 20 on-chip pull-up resistors which can be specified by means of software: 12 also used for segment pins: 8 n-ch open-drain 4 on-chip pull-up resistors which can be specified by mask option, 13 v withstand i/o pins voltage total 32 lcd controller/driver ? segment selection: 16/20/24 segments (can be changed to cmos i/o port in 4 time-unit; max. 8) ? display mode selection: static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias), 1/3 duty (1/3 bias), 1/4 duty (1/3 bias) ? on-chip split resistor for lcd drive can be specified by mask option timer 5 channels ? 8-bit timer/event counter: 3 channels (16-bit timer/event counter, carrier generator, timer with gate) ? basic interval timer/watchdog timer: 1 channel ? watch timer: 1 channel serial interface ? 3-wire serial i/o mode ... msb or lsb can be selected for transferring first bit ? 2-wire serial i/o mode ? sbi mode bit sequential buffer (bsb) 16 bits clock output (pcl) ? f , 524, 262, 65.5 khz (@ 4.19 mhz with main system clock) ? f , 750, 375, 93.8 khz (@ 6.0 mhz with main system clock) buzzer output (buz) ? 2, 4, 32 khz (@ 4.19 mhz with main system clock or @ 32.768 khz with subsystem clock) ? 2.93, 5.86, 46.9 khz (@ 6.0 mhz with main system clock) vectored interrupt external: 3, internal: 5 test input external: 1, internal: 1 system clock oscillator ? ceramic or crystal oscillator for main system clock oscillation ? crystal oscillator for subsystem clock oscillation standby function stop/halt mode supply voltage v dd = 1.8 to 5.5 v package ? 64-pin plastic qfp (14 14) ? 64-pin plastic lqfp (12 12) ? 64-pin plastic tqfp (12 12) 4 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 contents 1. pin configuration (top view) ................................................................................................. ... 6 2. block diagram ................................................................................................................ ................ 8 3. pin functions ................................................................................................................ ................... 9 3.1 port pins ................................................................................................................... ................... 9 3.2 non-port pins ............................................................................................................... ............. 11 3.3 pin i/o circuits ............................................................................................................ .............. 13 3.4 recommended connections of unused pins ........................................................................ 15 4. switching function between mk i mode and mk ii mode ................................................ 16 4.1 difference between mk i mode and mk ii mode ..................................................................... 16 4.2 setting method of stack bank select register (sbs) ........................................................... 17 5. memory configuration ......................................................................................................... .... 18 6. peripheral hardware function ........................................................................................... 23 6.1 digital i/o port ............................................................................................................ ............... 23 6.2 clock generator ............................................................................................................. ...........23 6.3 subsystem clock oscillator control functions .................................................................... 25 6.4 clock output circuit ........................................................................................................ ......... 26 6.5 basic interval timer/watchdog timer ..................................................................................... 27 6.6 watch timer ................................................................................................................. .............28 6.7 timer/event counter ......................................................................................................... ........ 29 6.8 serial interface ............................................................................................................ .............. 33 6.9 lcd controller/driver ....................................................................................................... ........ 35 6.10 bit sequential buffer ...................................................................................................... .......... 37 7. interrupt function and test function .............................................................................. 38 8. standby function ............................................................................................................. ...........40 9. reset function ............................................................................................................... .............. 41 10. mask option ................................................................................................................. .................. 44 11. instruction set ............................................................................................................. ............... 45 12. electrical specifications ................................................................................................... .... 59 13. characteristic curves (for reference only) ............................................................... 75 14. package drawings ............................................................................................................ ......... 78 15. recommended soldering conditions ................................................................................. 81 5 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 appendix a. m pd75308b, 753108 and 75p3116 functional list .............................................. 83 appendix b. development tools ................................................................................................. 85 appendix c. related documents ................................................................................................ 89 6 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 bias v lc0 v lc1 v lc2 p30/lcdcl p31/sync p32 p33 v ss p50 p51 p52 p53 p60/kr0 p61/kr1 p62/kr2 s12 s13 s14 s15 s16/p93 s17/p92 s18/p91 s19/p90 s20/p83 s21/p82 s22/p81 s23/p80 p23/buz p22/pcl/pto2 p21/pto1 p20/pto0 com3 com2 com1 com0 s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 p63/kr3 reset xt1 xt2 ic note x1 x2 v dd p00/int4 p01/sck p02/so/sb0 p03/si/sb1 p10/int0 p11/int1 p12/int2/ti1/ti2 p13/ti0 1. pin configuration (top view) ? 64-pin plastic qfp (14 14) m pd753104gc- -ab8, 753106gc- -ab8, 753108gc- -ab8 ? 64-pin plastic lqfp (12 12) m pd753104gk- -8a8, 753106gk- -8a8, 753108gk- -8a8 ? 64-pin plastic tqfp (12 12) m pd753104gk- -9et, 753106gk- -9et, 753108gk- -9et note connect the ic (internally connected) pin directly to v dd . 7 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 pin identification p00 to p03: port 0 v lc0 to v lc2 : lcd power supply 0 to 2 p10 to p13: port 1 bias: lcd power supply bias control p20 to p23: port 2 lcdcl: lcd clock p30 to p33: port 3 sync: lcd synchronization p50 to p53: port 5 ti0 to ti2: timer input 0 to 2 p60 to p63: port 6 pto0 to pto2: programmable timer output 0 to 2 p80 to p83: port 8 buz: buzzer clock p90 to p93: port 9 pcl: programmable clock kr0 to kr3: key return 0 to 3 int0, int1, int4: external vectored interrupt 0, 1, 4 sck: serial clock int2: external test input 2 si: serial input x1, x2: main system clock oscillation 1, 2 so: serial output xt1, xt2: subsystem clock oscillation 1, 2 sb0, sb1: serial data bus 0, 1 v dd : positive power supply reset: reset v ss : ground s0 to s23: segment output 0 to 23 ic: internally connected com0 to com3: common output 0 to 3 8 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 2. block diagram note the rom capacity depends on the product. watch timer intw f lcd basic interval timer/ watchdog timer intbt 8-bit timer/event counter #0 intt0 tout0 8-bit timer/event counter #1 8-bit timer/event counter #2 cascaded 16-bit timer/ event counter intt2 clocked serial interface intcsi tout0 int1 interrupt control bit seq. buffer (16) int0/p10 int1/p11 int4/p00 int2/p12/ti1/ti2 kr0/p60 to kr3/p63 4 si/sb1/p03 so/sb0/p02 sck/p01 ti1/ti2/p12/int2 pto1/p21 pto2/pcl/p22 intt1 ti0/p13 pto0/p20 buz/p23 program counter program memory note (rom) alu decode and control cy sp(8) sbs bank general reg. data memory (ram) 512 4 bits clock output control clock divider system clock generator main sub stand by control cpu clock f pcl/pto2/p22 x1 x2 xt1xt2 ic v dd v ss reset f lcd port0 4 p00 to p03 port1 p10 to p13 port2 p20 to p23 port3 p30 to p33 port5 p50 to p53 port6 p60 to p63 port8 p80 to p83 port9 p90 to p93 lcd controller/ driver 16 s0 to s15 4 s16/p93 to s19/p90 4 s20/p83 to s23/p80 4 com0 to com3 bias v lc0 v lc1 v lc2 sync/p31 lcdcl/p30 f x /2 n 4 4 4 4 4 4 4 tout0 9 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 3. pin functions 3.1 port pins (1/2) pin name i/o alternate function 8-bit after reset i/o circuit function i/o type note 1 p00 input int4 no input (b) p01 sck (f)-a p02 so/sb0 (f)-b p03 si/sb1 (m)-c p10 input int0 no input (b)-c p11 int1 p12 ti1/ti2/int2 p13 ti0 p20 i/o pto0 no input e-b p21 pto1 p22 pcl/pto2 p23 buz p30 i/o lcdcl no input e-b p31 sync p32 C p33 C p50 to p53 note 2 i/o C no m-d notes 1. characters in parentheses indicate the schmitt-triggered input. 2. if on-chip pull-up resistors are not specified by mask option (when used as n-ch open-drain input port), low-level input leakage current increases when input or bit manipulation instruction is executed. 4-bit input port (port0). an on-chip pull-up resistor can be specified by means of software in 3-bit units. 4-bit input port (port1). an on-chip pull-up resistor can be specified by means of software in 4-bit units. p10/int0 can select noise elimination circuit. 4-bit i/o port (port2). an on-chip pull-up resistor can be specified by means of software in 4-bit units. programmable 4-bit i/o port (port3). input/output can be specified in 1-bit units. an on-chip pull-up resistor can be specified by means of software in 4-bit units. n-ch open-drain 4-bit i/o port (port5). an on-chip pull-up resistor can be specified in 1-bit units (mask option). withstand voltage is 13 v in open-drain mode. high level (when pull- up resistors are provided) or high- impedance 10 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 3.1 port pins (2/2) pin name i/o alternate function 8-bit after reset i/o circuit function i/o type note 1 p60 i/o kr0 no input (f)-a p61 kr1 p62 kr2 p63 kr3 p80 i/o s23 yes input h p81 s22 p82 s21 p83 s20 p90 i/o s19 input h p91 s18 p92 s17 p93 s16 notes 1. characters in parentheses indicate the schmitt-triggered input. 2. when these pins are used as segment signal output pins, do not connect the on-chip pull-up resistor by means of software. programmable 4-bit i/o port (port6). input/output can be specified in 1-bit units. an on-chip pull-up resistor can be specified by means of software in 4-bit units. 4-bit i/o port (port8). an on-chip pull-up resistor can be specified by means of software in 4-bit units note 2 . 4-bit i/o port (port9). an on-chip pull-up resistor can be specified by means of software in 4-bit units note 2 . 11 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 3.2 non-port pins (1/2) pin name i/o alternate function after reset i/o circuit function type note 1 ti0 input p13 external event pulse input to the timer/event input (b)-c ti1 p12/int2/ti2 counter. ti2 p12/int2/ti1 pto0 output p20 timer/event counter output input e-b pto1 p21 pto2 p22/pcl pcl p22/pto2 clock output buz p23 optional frequency output (for buzzer output or system clock trimming) sck i/o p01 serial clock i/o input (f)-a so/sb0 p02 serial data output (f)-b serial data bus i/o si/sb1 p03 serial data input (m)-c serial data bus i/o int4 input p00 edge detection vectored interrupt input (both input (b) rising edge and falling edge detection) int0 input p10 input (b)-c int1 p11 int2 p12/ti1/ti2 kr0 to kr3 input p60 to p63 falling edge detection testable input input (f)-a s0 to s15 output C segment signal output note 2 g-a s16 to s19 output p93 to p90 segment signal output input h s20 to s23 output p83 to p80 segment signal output input h com0 to com3 output C common signal output note 2 g-b v lc0 to v lc2 C C lcd drive power C C on-chip split resistor is enabled (mask option). bias output C output for external split resistor disconnect note 3 C lcdcl note 4 output p30 clock output for externally expanded driver input e-b sync note 4 output p31 clock output for externally expanded driver input e-b synchronization notes 1. characters in parentheses indicate the schmitt-triggered input. 2. each display output selects the following v lcx as input source. s0 to s15: v lc1 , com0 to com2: v lc2 , com3: v lc0 3. when a split resistor is contained ........ low level when no split resistor is contained ...... high impedance 4. these pins are provided for future system expansion. at present, these pins are used only as pins p30 and p31. edge detection vectored noise elimination circuit/ interrupt input (detection asynchronous selection edge can be selected). int0/p10 can select noise elimination circuit. rising edge detection asynchronous testable input asynchronous 12 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 3.2 non-port pins (2/2) pin name i/o alternate function after reset i/o circuit function type note x1 input C crystal/ceramic connection pin for the main C C system clock oscillation. when the external clock is used, input the external clock to pin x1, and the inverted phase of the external clock to pin x2. xt1 input C C C xt2 C reset input C system reset input (low-level active) C (b) ic C C internally connected. connect directly to v dd .C C v dd C C positive power supply C C v ss C C ground potential C C note characters in parentheses indicate the schmitt-triggered input. crystal connection pin for the subsystem clock oscillation. when the external clock is used, input the external clock to pin xt1, and the inverted phase of the external clock to pin xt2. pin xt1 can be used as a 1-bit input (test) pin. x2 C 13 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 type a type b type d type e-b type b-c type f-a v dd in p-ch n-ch data output disable n-ch p-ch in out v dd p-ch output disable data p.u.r. enable type d type a in/out v dd p.u.r. enable p.u.r. p-ch in v dd p.u.r. p.u.r. enable p-ch in/out type d type b output disable data p.u.r. : pull-up resistor p.u.r. : pull-up resistor p.u.r. : pull-up resistor schmitt-triggered input with hysteresis characteristics cmos standard input buffer push-pull output that can be placed in output high-impedance (both p-ch and n-ch off). p.u.r. v dd 3.3 pin i/o circuits the m pd753108 pin input/output circuits are shown schematically. (1/2) 14 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 type f-b type h type g-a type m-c type m-d v dd p.u.r enable p.u.r. p-ch p-ch v dd n-ch output disable (p) data output disable output disable (n) in/out p.u.r. : pull-up resistor data output disable p.u.r. enable p.u.r. v dd p-ch in/out n-ch p.u.r. : pull-up resistor type g-b seg data data output disable type g-a type e-b in/out n-ch n-ch v lc0 v lc1 seg data v lc2 out p-ch n-ch p-ch n-ch p-ch n-ch n-ch p-ch v lc0 v lc1 p-ch n-ch out n-ch v lc2 n-ch com data p-ch p-ch n-ch p-ch n-ch p-ch n-ch in/out p.u.r. (mask option) data output disable n-ch p-ch input instruction (+13 v withstand voltage) the pull-up resistor operates only when an input instruction is executed (current flows from v dd to the pin when the pin is low). v dd v dd p.u.r. voltage limitation circuit note (+13 v withstand voltage) note (2/2) 15 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 3.4 recommended connections of unused pins table 3-1. list of recommended connections for unused pins pin name recommended connection p00/int4 connect to v ss or v dd . p01/sck at input: independently connect to v ss or v dd via a resistor. p02/so/sb0 at output: leave open. p03/si/sb1 connect to v ss . p10/int0, p11/int1 connect to v ss or v dd . p12/ti1/ti2/int2 p13/ti0 p20/pto0 at input: independently connect to v ss or v dd via a resistor. p21/pto1 at output: leave open. p22/pcl/pto2 p23/buz p30/lcdcl p31/sync p32 p33 p50 to p53 at input: connect to v ss . at output: connect to v ss (do not connect a pull-up resistor of mask option). p60/kr0 to p63/kr3 at input: independently connect to v ss or v dd via a resistor. at output: leave open. s0 to s15 leave open. com0 to com3 s16/p93 to s19/p90 at input: independently connect to v ss or v dd via a resistor. s20/p83 to s23/p80 at output: leave open. v lc0 to v lc2 connect to v ss . bias only if all of v lc0 to v lc2 are unused, connect to v ss . in other cases, leave open. xt1 note connect to v ss . xt2 note leave open. ic connect directly to v dd . note when the subsystem clock is not used, specify sos.0 = 1 (so as not to use the on-chip feedback resistor). 16 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 4. switching function between mk i mode and mk ii mode 4.1 difference between mk i mode and mk ii mode the cpu of the m pd753108 has the following two modes: mk i and mk ii, either of which can be selected. the mode can be switched by bit 3 of the stack bank select register (sbs). ? mk i mode: upward compatible with the m pd75308b. can be used in the 75xl cpu with a rom capacity of up to 16 kb. ? mk ii mode: incompatible with the m pd75308b. can be used in all the 75xl cpus including those products whose rom capacity is more than 16 kb. table 4-1. differences between mk i mode and mk ii mode mk i mode mk ii mode number of stack bytes 2 bytes 3 bytes for subroutine instructions bra !addr1 instruction not available available calla !addr1 instruction call !addr instruction 3 machine cycles 4 machine cycles callf !faddr instruction 2 machine cycles 3 machine cycles caution the mk ii mode supports a program area exceeding 16 kb for the 75x and 75xl series. therefore, this mode is effective for enhancing software compatibility with products exceeding 16 kb. when the mk ii mode is selected, the number of stack bytes used during execution of subroutine call instructions increases by one byte per stack compared to the mk i mode. when the call !addr and callf !faddr instructions are used, the machine cycle becomes longer by one machine cycle. therefore, use the mk i mode if the ram efficiency and processing performance are more important than software compatibility. 17 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 caution since sbs. 3 is set to 1 after a reset signal is generated, the cpu operates in the mk i mode. when executing an instruction in the mk ii mode, set sbs. 3 to 0 to select the mk ii mode. 4.2 setting method of stack bank select register (sbs) switching between the mk i mode and mk ii mode can be done by the stack bank select register (sbs). figure 4-1 shows the format. the sbs is set by a 4-bit memory manipulation instruction. when using the mk i mode, the sbs must be initialized to 100 b note at the beginning of a program. when using the mk ii mode, it must be initialized to 000 b note . note set the desired value in the position. figure 4-1. stack bank select register format sbs3 sbs2 sbs1 sbs0 3210 symbol sbs address f84h 00 01 0 1 0 memory bank 0 memory bank 1 other than above setting prohibited 0 must be set in the bit 2 position. stack area specification mk ii mode mk i mode mode switching specification 18 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 5. memory configuration program memory (rom) .... 4096 8 bits ( m pd753104) .... 6144 8 bits ( m pd753106) .... 8192 8 bits ( m pd753108) ? addresses 0000h and 0001h vector table wherein the program start address and the values set for the rbe and mbe at the time a reset signal is generated are written. reset start is possible from any address. ? addresses 0002h to 000dh vector table wherein the program start address and the values set for the rbe and mbe by each vectored interrupt are written. interrupt processing can start from any address. ? addresses 0020h to 007fh table area referenced by the geti instruction note . note the geti instruction realizes a 1-byte instruction on behalf of any 2-byte instruction, 3-byte instruction, or two 1-byte instructions. it is used to decrease the number of program steps. data memory (ram) ? data area ... 512 words 4 bits (000h to 1ffh) ? peripheral hardware area ... 128 words 4 bits (f80h to fffh) 19 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 figure 5-1. program memory map (1/3) (a) m pd753104 note can be used in mk ii mode only. remark in addition to the above, a branch can be taken to the address indicated by changing only the low-order eight bits of pc by executing the br pcde or br pcxa instruction. 000h address 7654 mbe rbe 0 0 internal reset start address (high-order 4 bits) 0 002h mbe rbe 0 0 intbt/int4 (high-order 4 bits) start address 004h mbe rbe 0 0 int0 (high-order 4 bits) start address 006h mbe rbe 0 0 int1 (high-order 4 bits) start address 008h mbe rbe 0 0 intcsi (high-order 4 bits) start address 00ah mbe rbe 0 0 intt0 (high-order 4 bits) start address 00ch mbe rbe 0 0 intt1/intt2 (high-order 4 bits) start address 020h 07fh 080h 7ffh 800h fffh geti instruction reference table (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) callf !faddr instruction entry address brcb !caddr instruction branch address branch destination address and subroutine entry address when geti instruction is executed internal reset start address intbt/int4 start address int0 start address int1 start address intcsi start address intt0 start address intt1/intt2 start address branch address of br bcxa, br bcde, br !addr, bra !addr1 note or calla !addr1 note instruction call !addr instruction subroutine entry address br $addr instruction relative branch address ?5 to ?, +2 to +16 20 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 0000h address 0002h mbe rbe 0 intbt/int4 (high-order 5 bits) start address 0004h mbe rbe 0 int0 (high-order 5 bits) start address 0006h mbe rbe 0 int1 (high-order 5 bits) start address 0008h mbe rbe 0 intcsi (high-order 5 bits) start address 000ah mbe rbe 0 intt0 (high-order 5 bits) start address 0020h 007fh 0080h 07ffh 0800h mbe rbe 0 internal reset start address (high-order 5 bits) 0fffh 1000h 17ffh geti instruction reference table 000ch mbe rbe 0 intt1/intt2 (high-order 5 bits) start address (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) callf !faddr instruction entry address brcb !caddr instruction branch address branch address of br bcxa, br bcde, br !addr, bra !addr1 note or calla !addr1 note instruction call !addr instruction subroutine entry address br $addr instruction relative branch address ?5 to ?, +2 to +16 branch destination address and subroutine entry address when geti instruction is executed brcb !caddr instruction branch address 765 0 internal reset start address intbt/int4 int0 int1 intcsi intt0 intt1/intt2 start address start address start address start address start address start address figure 5-1. program memory map (2/3) (b) m pd753106 note can be used in mk ii mode only. remark in addition to the above, a branch can be taken to the address indicated by changing only the low-order eight bits of pc by executing the br pcde or br pcxa instruction. 21 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 figure 5-1. program memory map (3/3) (c) m pd753108 note can be used in mk ii mode only. remark in addition to the above, a branch can be taken to the address indicated by changing only the low-order eight bits of pc by executing the br pcde or br pcxa instruction. 0000h address 0002h mbe rbe 0 intbt/int4 (high-order 5 bits) start address 0004h mbe rbe 0 int0 (high-order 5 bits) start address 0006h mbe rbe 0 int1 (high-order 5 bits) start address 0008h mbe rbe 0 intcsi (high-order 5 bits) start address 000ah mbe rbe 0 intt0 (high-order 5 bits) start address 0020h 007fh 0080h 07ffh 0800h mbe rbe 0 internal reset start address (high-order 5 bits) 0fffh 1000h 1fffh geti instruction reference table 000ch mbe rbe 0 intt1/intt2 (high-order 5 bits) start address (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) callf !faddr instruction entry address brcb !caddr instruction branch address branch address of br bcxa, br bcde, br !addr, bra !addr1 note or calla !addr1 note instruction call !addr instruction subroutine entry address br $addr instruction relative branch address ?5 to ?, +2 to +16 branch destination address and subroutine entry address when geti instruction is executed brcb !caddr instruction branch address 765 0 internal reset start address intbt/int4 int0 int1 intcsi intt0 intt1/intt2 start address start address start address start address start address start address 22 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 figure 5-2. data memory map note either memory bank 0 or 1 can be selected for the stack area. data area static ram (512 4) stack area note general-purpose register area 000h 01fh 0ffh 100h 1dfh 1e0h 1f7h 1f8h 1ffh f80h fffh display data memory peripheral hardware area data memory memory bank 0 (32 4) 256 4 (224 4) 256 4 (224 4) (24 4) (8 4) not incorporated 128 4 15 1 23 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 6. peripheral hardware function 6.1 digital i/o port there are three kinds of i/o port. ? cmos input ports (port 0, 1): 8 ? cmos i/o ports (port 2, 3, 6, 8, 9): 20 ? n-ch open-drain i/o ports (port 5): 4 total 32 table 6-1. types and features of digital ports port name function operation and features remarks port0 4-bit input when the serial interface function is used, the alternate also used for the int4, sck, function pins function as output ports depending on the so/sb0, si/sb1 pins. operation mode. port1 4-bit input only port. also used for the int0 to int2/ti1/ti2, ti0 pins. port2 4-bit i/o input/output can be specified in 4-bit units. also used for the pto0 to pto2/pcl, buz pins. port3 input/output can be specified in 1-bit units. also used for the lcdcl, sync pins. port5 4-bit i/o input/output can be specified in 4-bit units. (n-ch open- on-chip pull-up resistor can be specified in 1-bit units drain, 13 v by mask option. withstand voltage) port6 4-bit i/o input/output can be specified in 1-bit units. also used for the kr0 to kr3 pins. port8 input/output can be ports 8 and 9 are paired also used for the s20 to s23 pins. port9 specified in 4-bit units. and data can be input/ also used for the s16 to s19 pins. output in 8-bit units. 6.2 clock generator the clock generator is a device that generates the clock which is supplied to peripheral hardware on the cpu and is configured as shown in figure 6-1. the clock generator operates according to how the processor clock control register (pcc) and system clock control register (scc) are set. there are two kinds of clocks, main system clock and subsystem clock. the instruction execution time can also be changed. ? 0.95, 1.91, 3.81, 15.3 m s (main system clock: @ 4.19 mhz operation) ? 0.67, 1.33, 2.67, 10.7 m s (main system clock: @ 6.0 mhz operation) ? 122 m s (subsystem clock: @ 32.768 khz operation) 24 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 v dd v dd xt1 x1 xt2 x2 f xt f x subsystem clock oscillator main system clock oscillator 4 halt note stop note wm.3 scc scc3 scc0 pcc0 pcc1 pcc2 pcc3 pcc2, pcc3 clear stop f/f q s r oscillation stop halt f/f s r wait release signal from bt reset signal standby release signal from interrupt control circuit ?cpu ?int0 noise elimination circuit ?clock output circuit f 1/4 divider 1/1 to 1/4096 divider 1/2 1/4 1/16 ?basic interval timer (bt) ?timer/event counter ?serial interface ?watch timer ?lcd controller/driver ?int0 noise elimination circuit ?clock output circuit lcd controller/driver watch timer pcc q selector selector internal bus figure 6-1. clock generator block diagram note instruction execution remarks 1. f x = main system clock frequency 2. f xt = subsystem clock frequency 3. f = cpu clock 4. pcc: processor clock control register 5. scc: system clock control register 6. one clock cycle (t cy ) of the cpu clock is equal to one machine cycle of the instruction. 25 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 6.3 subsystem clock oscillator control functions the m pd753108 subsystem clock oscillator has the following two control functions. ? selects by means of software whether an on-chip feedback resistor is to be used or not note . ? reduces current consumption by decreasing the drive current of the on-chip inverter when the supply voltage is high (v dd 3 2.7 v). note when the subsystem clock is not used, set sos.0 to 1 (so as not to use the on-chip feedback resistor) by software, connect xt1 to v ss , and leave xt2 open. this makes it possible to reduce the current consumption in the subsystem clock oscillator. the above functions can be used by switching the bits 0 and 1 of the sub-oscillator control register (sos). (see figure 6-2.) figure 6-2. subsystem clock oscillator feedback resistor sos.0 sos.1 xt1 xt2 inverter v dd 26 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 6.4 clock output circuit the clock output circuit is provided to output the clock pulses from the p22/pto2/pcl pin to the remote control wave outputs and peripheral lsis. clock output (pcl): f , 524, 262, 65.5 khz (main system clock: @ 4.19 mhz operation) f , 750, 375, 93.8 khz (main system clock: @ 6.0 mhz operation) figure 6-3. clock output circuit block diagram remark special care has been taken in designing the chip so that small-width pulses may not be output when switching clock output enable/disable. from clock generator f f x /2 3 f x /2 4 f x /2 6 selector clom3 0 clom1 clom0 4 clom p22 output latch port 2 i/o mode specification bit port2.2 bit 2 of pmgb internal bus output buffer pcl/pto2/p22 selector from timer/event counter (channel 2) 27 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 6.5 basic interval timer/watchdog timer the basic interval timer/watchdog timer has the following functions. interval timer operation to generate a reference time interrupt watchdog timer operation to detect a runaway of program and reset the cpu selects and counts the wait time when the standby mode is released reads the contents of counting figure 6-4. basic interval timer/watchdog timer block diagram note instruction execution from clock generator f x /2 5 f x /2 7 f x /2 9 f x /2 12 mpx btm3 btm2 btm1 btm0 btm 4 set1 note internal bus 81 basic interval timer (8-bit frequency divider) clear bt wait release signal when standby is released. set clear 3 wdtm set1 note internal reset signal vectored interrupt request signal bt interrupt request flag irqbt 28 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 6.6 watch timer the m pd753108 has one watch timer channel which has the following functions. sets the test flag (irqw) at 0.5-second intervals. the standby mode can be released by the irqw. 0.5-second interval can be created by both the main system clock (4.19 mhz) and subsystem clock (32.768 khz). convenient for program debugging and checking as interval becomes 128 times longer (3.91 ms) with the fast feed mode. outputs the frequencies (2.048, 4.096, 32.768 khz) to the p23/buz pin, usable for buzzer and trimming of system clock oscillation frequencies. clears the frequency divider to make the watch start with zero seconds. figure 6-5. watch timer block diagram remark the values enclosed in parentheses are applied when f x = 4.19 mhz and f xt = 32.768 khz. from clock generator selector f x 128 (32.768 khz) f xt (32.768 khz) f w (32.768 khz) divider 4 khz 2 khz f w 2 3 f w 2 4 clear selector f w 2 7 f w 2 6 (512 hz : 1.95 ms) (256 hz : 3.91 ms) f w 2 14 selector 2 hz 0.5 sec irqw set signal intw f lcd output buffer bit 2 of pmgb port2.3 wm wm7 0 wm5 wm4 wm3 wm2 wm1 wm0 p23 output latch port 2 i/o mode 8 internal bus bit test instruction p23/buz 29 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 6.7 timer/event counter the m pd753108 has three channels of timer/event counters. its configuration is shown in figures 6-6 to 6-8. the timer/event counter has the following functions. programmable interval timer operation square wave output of any frequency to the pton pin (n = 0 to 2) event counter operation divides the frequency of signal input via the tin pin to 1-nth of the original signal and outputs the divided frequency to the pton pin (frequency divider operation). supplies the serial shift clock to the serial interface circuit. reads the count value. the timer/event counter operates in the following four modes as set by the mode register. table 6-2. operation modes of timer/event counter channel channel 0 channel 1 channel 2 mode 8-bit timer/event counter mode yes yes yes gate control function no note no yes pwm pulse generator mode no no yes 16-bit timer/event counter mode no yes gate control function no note yes carrier generator mode no yes note used for gate control signal generation 30 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 port1.3 input buffer ti0/p13 from clock generator mpx f x /2 4 f x /2 6 f x /2 8 f x /2 10 tm06 tm05 tm04 tm03 tm02 0 888 8 8 tm0 set1 note modulo register (8) comparator (8) count register (8) tmod0 t0 cp timer operation start clear match tout0 tout f/f reset t0 enable flag p20 output latch port 2 i/o mode toe0 port2.0 bit 2 of pmgb to serial interface pto0/p20 intt0 irqt0 set signal reset irqt0 clear signal to timer/event counter (channel 2) internal bus output buffer figure 6-6. timer/event counter (channel 0) block diagram note instruction execution caution when setting data to tm0, be sure to set bit 1 to 0. 31 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 port1.2 input buffer ti1/ti2/p12/int2 timer/event counter (channel 2) output from clock generator mpx f x /2 5 f x /2 6 f x /2 8 f x /2 10 f x /2 12 tm16 tm15 tm14 tm13 tm12 tm11 tm10 tm1 set1 note decoder 16-bit timer/event counter mode cp timer operation start selector clear 8 8 8 8 modulo register (8) comparator (8) count register (8) timer/event counter (channel 2) match signal (when 16-bit timer/event counter mode) timer/event counter (channel 2) comparator (when 16-bit timer/event counter mode) timer/event counter (channel 2) reload signal t1 tmod1 match tout f/f reset t1 enable flag p21 output latch port 2 i/o mode intt1 irqt1 set signal irqt1 clear signal reset toe1 port2.1 bit 2 of pmgb p21/pto1 output buffer internal bus figure 6-7. timer/event counter (channel 1) block diagram note instruction execution 32 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 port1.2 input buffer ti1/ti2/p12/int2 from clock generator mpx f x /2 10 f x /2 8 f x /2 6 f x /2 4 f x /2 f x tm25 tm26 tm24 tm23 tm22 tm21 tm20 tm2 set1 note 8 8 tc2 decoder high-level period setting modulo register (8) modulo register (8) tgce toe2 remc nrzb nrz reload mpx (8) comparator (8) count register (8) 8 8 clear 16-bit timer/event counter mode timer operation start timer/event counter (channel 1) match signal (when 16-bit timer/event counter mode) timer/event counter (channel 1) clear signal (when 16-bit timer/event counter mode) timer/event counter (channel 1) match signal (when carrier generator mode) match overflow carrier generator mode port2.2 bit 2 of pmgb p22 output latch output buffer p22/pcl/pto2 timer/event counter (channel 1) clock input intt2 irqt2 set signal irqt2 clear signal reset t2 tmod2 tmod2h internal bus cp timer event counter (channel 0) tout f/f reset 8 8 8 selector selector selector port 2 i/o tout f/f 8 from clock output circuit figure 6-8. timer/event counter (channel 2) block diagram note instruction execution 33 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 6.8 serial interface the m pd753108 incorporates a clock-synchronous 8-bit serial interface. the serial interface can be used in the following four modes. ? operation stop mode ? 3-wire serial i/o mode ? 2-wire serial i/o mode ? sbi mode 34 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 figure 6-9. serial interface block diagram internal bus 8 8 8 8/4 bit manipulation bit test sbic slave address register (sva) address comparator shift register (sio) (8) (8) (8) relt cmdt so latch set clr dq csim p03/si/sb1 p02/so/sb0 p01/sck p01 output iatch bus release/ command/ acknowledge detection circuit reld cmdd ackd ackt serial clock counter serial clock control circuit serial clock selector intcsi control circuit acke bsye busy/ acknowledge output circuit intcsi irqcsi set signal f x /2 3 f x /2 4 f x /2 6 tout0 (from timer/event counter (channel 0)) bit test match selector selector external sck 35 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 6.9 lcd controller/driver the m pd753108 incorporates a display controller which generates segment and common signals according to the display data memory contents and incorporates segment and common drivers which can drive the lcd panel directly. the m pd753108 lcd controller/driver has the following functions: display data memory is read automatically by dma operation and segment and common signals are generated. display mode can be selected from among the following five: <1> static <2> 1/2 duty (time-divided by 2), 1/2 bias <3> 1/3 duty (time-divided by 3), 1/2 bias <4> 1/3 duty (time-divided by 3), 1/3 bias <5> 1/4 duty (time-divided by 4), 1/3 bias a frame frequency can be selected from among four in each display mode. a maximum of 24 segment signal output pins (s0 to s23) and four common signal output pins (com0 to com3). the segment signal output pins (s0 to s23) can be changed to the i/o ports (port8 and port9). split resistor can be incorporated to supply lcd drive power (mask option). ? various bias methods and lcd drive voltages are applicable. ? when display is off, current flowing through the split resistor is cut. display data memory not used for display can be used for normal data memory. it can also operate by using the subsystem clock. 36 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 figure 6-10. lcd controller/driver block diagram port 8 output latch 3210 port 9 output latch port mode register group c 3210 0 1 lcd/port selection register decoder 1f7h 3210 1f0h 3210 1efh 3210 1e0h 3210 3210 3210 3210 3210 display mode register display control register timing controller port 3 output latch 10 port mode register group a 10 segment driver segment driver common driver lcd drive voltage control 0123 port 8 i/o buffer 0123 port 9 i/o buffer s23/p80 s16/p93 s15 s0 com3 com2 com1 com0 v lc2 v lc1 v lc0 p31/sync p30/lcdcl f lcd 44 4 4 8 4 4 8 4 4 4 internal bus lcd drive mode switching 37 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 6.10 bit sequential buffer ....... 16 bits the bit sequential buffer (bsb) is a special data memory for bit manipulation and the bit manipulation can be easily performed by changing the address specification and bit specification in sequence, therefore it is useful when processing a long data bit-wise. figure 6-11. bit sequential buffer format remarks 1. in the pmem.@l addressing, the specified bit moves corresponding to the l register. 2. in the pmem.@l addressing, the bsb can be manipulated regardless of mbe/mbs specification. address bit symbol l register l = fh l = ch l = bh l = 8h l = 7h l = 4h l = 3h l = 0h decs l incs l bsb3 bsb2 bsb1 bsb0 3210321032103210 fc3h fc2h fc1h fc0h 38 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 7. interrupt function and test function the m pd753108 has eight types of interrupt sources and two types of test sources. of these test sources, int2 has two types of edge detection testable inputs. the interrupt control circuit of the m pd753108 has the following functions. (1) interrupt function ? vectored interrupt function for hardware control, enabling/disabling the interrupt acceptance by the interrupt enable flag (ie ) and interrupt master enable flag (ime). ? can set any interrupt start address. ? multiple interrupts wherein the order of priority can be specified by the interrupt priority select register (ips). ? test function of interrupt request flag (irq ). an interrupt generation can be checked by software. ? release the standby mode. an interrupt to be released can be selected by the interrupt enable flag. (2) test function ? test request flag (irq ) generation can be checked by software. ? release the standby mode. the test source to be released can be selected by the test enable flag. 39 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 im2 internal bus interrupt enable flag (ie xxx ) irqbt irq4 irq0 irq1 irqcsi irqt0 irqt1 irqt2 irqw irq2 intcsi intt0 intt1 intt2 intw both edge detector edge detector edge detector selec- tor int4/p00 int0/p10 int1/p11 int2/p12 kr0/p60 kr3/p63 rising edge detector falling edge detector selec- tor im2 standby release signal priority control circuit vector table address generator decoder ime ips ist0 vrqn note 214 intbt ist1 im0 im1 note noise elimination circuit (standby release is disabled when noise elimination circuit is selected.) figure 7-1. interrupt control circuit block diagram 40 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 8. standby function in order to reduce power dissipation while a program is in a standby mode, two types of standby modes (stop mode and halt mode) are provided for the m pd753108. table 8-1. operation status in standby mode item mode stop mode halt mode set instruction stop instruction halt instruction system clock when set settable only when the main system settable both by the main system clock clock is used. and subsystem clock. operation clock generator main system clock stops oscillation. only the cpu clock f halts (oscillation status continues). basic interval timer/ operation stops. operable only when the main system watchdog timer clock is oscillated. bt mode : irqbt is set in the reference time interval wt mode : reset signal is generated by bt overflow serial interface operable only when an external sck operable only when an external sck input input is selected as the serial clock. is selected as the serial clock or when the main system clock is oscillated. timer/event counter operable only when a signal input to the operable only when a signal input to the ti0 to ti2 pins is specified as the count ti0 to ti2 pins is specified as the count clock. clock or when the main system clock is oscillated. watch timer operable when f xt is selected as the operable. count clock. lcd controller/driver operable only when f xt is selected as the operable. lcdcl. external interrupt the int1, 2, and 4 are operable. only the int0 is not operated note . cpu the operation stops. release signal ? interrupt request signal sent from the operable hardware enabled by the interrupt enable flag ? test request signal sent from the test source enabled by the test enable flag ? reset pin note can operate only when the noise elimination circuit is not used (im02 = 1) by bit 2 of the edge detection mode register (im0). 41 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 generation of the reset signal initializes each hardware as listed in table 9-1. figure 9-2 shows the timing chart of the reset operation. figure 9-2. reset operation by reset signal generation note the following two times can be selected by the mask option. 2 17 /f x (21.8 ms: @ 6.00 mhz operation, 31.3 ms: @ 4.19 mhz operation) 2 15 /f x (5.46 ms: @ 6.00 mhz operation, 7.81 ms: @ 4.19 mhz operation) 9. reset function there are two reset inputs: external reset signal (reset) and reset signal sent from the basic interval timer/ watchdog timer. when either one of the reset signals are input, an internal reset signal is generated. figure 9- 1 shows the configuration of the above two inputs. figure 9-1. configuration of reset function reset internal reset signal reset signal sent from the basic interval timer/watchdog timer wdtm internal bus operation mode or standby mode wait note reset signal generated operation mode halt mode internal reset operation 42 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 table 9-1. status of each hardware after reset (1/2) hardware reset signal generation reset signal generation in the standby mode in operation program counter (pc) m pd753104 sets the low-order 4 bits of sets the low-order 4 bits of program memorys address program memorys address 0000h to the pc11 to pc8 and 0000h to the pc11 to pc8 and the contents of address 0001h the contents of address 0001h to the pc7 to pc0. to the pc7 to pc0. m pd753106, sets the low-order 5 bits of sets the low-order 5 bits of m pd753108 program memorys address program memorys address 0000h to the pc12 to pc8 and 0000h to the pc12 to pc8 and the contents of address 0001h the contents of address 0001h to the pc7 to pc0. to the pc7 to pc0. psw carry flag (cy) held undefined skip flag (sk0 to sk2) 0 0 interrupt status flag (ist0, ist1) 0 0 bank enable flag (mbe, rbe) sets the bit 6 of program sets the bit 6 of program memorys address 0000h to the memorys address 0000h to the rbe and bit 7 to the mbe. rbe and bit 7 to the mbe. stack pointer (sp) undefined undefined stack bank select register (sbs) 1000b 1000b data memory (ram) held undefined general-purpose register (x, a, h, l, d, e, b, c) held undefined bank select register (mbs, rbs) 0, 0 0, 0 basic interval counter (bt) undefined undefined timer/watchdog mode register (btm) 0 0 timer watchdog timer enable flag (wdtm) 0 0 timer/event counter (t0) 0 0 counter (t0) modulo register (tmod0) ffh ffh mode register (tm0) 0 0 toe0, tout f/f 0, 0 0, 0 timer/event counter (t1) 0 0 counter (t1) modulo register (tmod1) ffh ffh mode register (tm1) 0 0 toe1, tout f/f 0, 0 0, 0 timer/event counter (t2) 0 0 counter (t2) modulo register (tmod2) ffh ffh high-level period setting modulo ffh ffh register (tmod2h) mode register (tm2) 0 0 toe2, tout f/f 0, 0 0, 0 remc, nrz, nrzb 0, 0, 0 0, 0, 0 tgce 0 0 watch timer mode register (wm) 0 0 43 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 table 9-1. status of each hardware after reset (2/2) hardware reset signal generation reset signal generation in the standby mode in operation serial interface shift register (sio) held undefined operation mode register (csim) 00 sbi control register (sbic) 0 0 slave address register (sva) held undefined clock generator, processor clock control register (pcc) 0 0 clock output system clock control register (scc) 0 0 circuit clock output mode register (clom) 0 0 sub-oscillator control register (sos) 0 0 lcd controller/ display mode register (lcdm) 0 0 driver display control register (lcdc) 0 0 lcd/port selection register (lps) 0 0 interrupt interrupt request flag (irqxxx) reset (0) reset (0) function interrupt enable flag (iexxx) 0 0 interrupt priority selection register (ips) 00 int0, 1, 2 mode registers (im0, im1, im2) 0, 0, 0 0, 0, 0 digital port output buffer off off output latch cleared (0) cleared (0) i/o mode registers (pmga, b, c) 0 0 pull-up resistor setting register (poga, b) 00 bit sequential buffer (bsb0 to bsb3) held undefined 44 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 10. mask option the m pd753108 has the following mask options. mask options of p50 to p53 selects whether or not to internally connect a pull-up resistor. <1> connect pull-up resistor internally in 1-bit units. <2> do not connect pull-up resistor internally. v lc0 to v lc2 pins, bias pin mask option selects whether or not to internally connect lcd-driving split resistors. <1> do not connect split resistor internally. <2> connect four 10 k w (typ.) split resistors simultaneously internally. <3> connect four 100 k w (typ.) split resistors simultaneously internally. standby function mask option selects the wait time with the reset signal. <1> 2 17 /fx (21.8 ms: @ fx = 6.0 mhz operation, 31.3 ms: @ fx = 4.19 mhz operation) <2> 2 15 /fx (5.46 ms: @ fx = 6.0 mhz operation, 7.81 ms: @ fx = 4.19 mhz operation) 45 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 11. instruction set (1) expression formats and description methods of operands the operand is described in the operand column of each instruction in accordance with the description method for the operand expression format of the instruction. for details, refer to ra75x assembler package users manuallanguage (u12385e) . if there are several elements, one of them is selected. capital letters and the + and C symbols are key words and are described as they are. for immediate data, appropriate numbers and labels are described. instead of the labels such as mem, fmem, pmem, and bit, the symbols of the register flags can be described. however, there are restrictions in the labels that can be described for fmem and pmem. for details, see users manual . expression description method format reg x, a, b, c, d, e, h, l reg1 x, b, c, d, e, h, l rp xa, bc, de, hl rp1 bc, de, hl rp2 bc, de rp' xa, bc, de, hl, xa', bc', de', hl' rp'1 bc, de, hl, xa', bc', de', hl' rpa hl, hl+, hlC, de, dl rpa1 de, dl n4 4-bit immediate data or label n8 8-bit immediate data or label mem 8-bit immediate data or label note bit 2-bit immediate data or label fmem fb0h to fbfh, ff0h to fffh immediate data or label pmem fc0h to fffh immediate data or label addr 0000h to 0fffh immediate data or label ( m pd753104) 0000h to 17ffh immediate data or label ( m pd753106) 0000h to 1fffh immediate data or label ( m pd753108) addr1 0000h to 0fffh immediate data or label ( m pd753104) (mk ii mode only) 0000h to 17ffh immediate data or label ( m pd753106) 0000h to 1fffh immediate data or label ( m pd753108) caddr 12-bit immediate data or label faddr 11-bit immediate data or label taddr 20h to 7fh immediate data (where bit0 = 0) or label portn port0 to port3, port5, port6, port8, port9 iexxx iebt, iet0 to iet2, ie0 to ie2, ie4, iecsi, iew rbn rb0 to rb3 mbn mb0, mb1, mb15 note mem can be only used for even address in 8-bit data processing. 46 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 (2) legend in explanation of operation a: a register, 4-bit accumulator b: b register c: c register d: d register e: e register h: h register l: l register x: x register xa: xa register pair; 8-bit accumulator bc: bc register pair de: de register pair hl: hl register pair xa: xa expanded register pair bc: bc expanded register pair de: de expanded register pair hl: hl expanded register pair pc: program counter sp: stack pointer cy: carry flag, bit accumulator psw: program status word mbe: memory bank enable flag rbe: register bank enable flag portn: port n (n = 0 to 3, 5, 6, 8, 9) ime: interrupt master enable flag ips: interrupt priority selection register ie : interrupt enable flag rbs: register bank selection register mbs: memory bank selection register pcc: processor clock control register .: separation between address and bit ( ): the contents addressed by h: hexadecimal data 47 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 (3) explanation of symbols under addressing area column *1 mb = mbembs (mbs = 0, 1, 15) *2 mb = 0 *3 mbe = 0 : mb = 0 (000h to 07fh) mb = 15 (f80h to fffh) data memory addressing mbe = 1 : mb = mbs (mbs = 0, 1, 15) *4 mb = 15, fmem = fb0h to fbfh, ff0h to fffh *5 mb = 15, pmem = fc0h to fffh *6 m pd753104 addr = 000h to fffh m pd753106 addr = 0000h to 17ffh m pd753108 addr = 0000h to 1fffh *7 addr = (current pc) C 15 to (current pc) C 1 (current pc) + 2 to (current pc) + 16 addr1 = (current pc) C 15 to (current pc) C 1 (current pc) + 2 to (current pc) + 16 *8 m pd753104 caddr = 000h to fffh m pd753106 caddr = 0000h to 0fffh (pc 12 = 0) or program memory addressing 1000h to 17ffh (pc 12 = 1) m pd753108 caddr = 0000h to 0fffh (pc 12 = 0) or 1000h to 1fffh (pc 12 = 1) *9 faddr = 0000h to 07ffh *10 taddr = 0020h to 007fh *11 m pd753104 addr1 = 000h to fffh m pd753106 addr1 = 0000h to 17ffh m pd753108 addr1 = 0000h to 1fffh remarks 1. mb indicates memory bank that can be accessed. 2. in *2, mb = 0 independently of how mbe and mbs are set. 3. in *4 and *5, mb = 15 independently of how mbe and mbs are set. 4. *6 to *11 indicate the areas that can be addressed. 48 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 (4) explanation of number of machine cycles column s denotes the number of machine cycles required by skip operation when a skip instruction is executed. the value of s varies as follows. ? when no skip is made: s = 0 ? when the skipped instruction is a 1- or 2-byte instruction: s = 1 ? when the skipped instruction is a 3-byte instruction note : s = 2 note 3-byte instruction: br !addr, bra !addr1, call !addr or calla !addr1 instruction caution the geti instruction is skipped in one machine cycle. one machine cycle is equal to one cycle of cpu clock f (= t cy ); time can be selected from among four types by setting pcc. 49 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area transfer mov a, #n4 1 1 a n4 string effect a reg1, #n4 2 2 reg1 n4 xa, #n8 2 2 xa n8 string effect a hl, #n8 2 2 hl n8 string effect b rp2, #n8 2 2 rp2 n8 a, @hl 1 1 a (hl) *1 a, @hl+ 1 2+s a (hl), then l l+1 *1 l = 0 a, @hlC 1 2+s a (hl), then l lC1 *1 l = fh a, @rpa1 1 1 a (rpa1) *2 xa, @hl 2 2 xa (hl) *1 @hl, a 1 1 (hl) a*1 @hl, xa 2 2 (hl) xa *1 a, mem 2 2 a (mem) *3 xa, mem 2 2 xa (mem) *3 mem, a 2 2 (mem) a*3 mem, xa 2 2 (mem) xa *3 a, reg 2 2 a reg xa, rp' 2 2 xa rp' reg1, a 2 2 reg1 a rp'1, xa 2 2 rp'1 xa xch a, @hl 1 1 a ? (hl) *1 a, @hl+ 1 2+s a ? (hl), then l l+1 *1 l = 0 a, @hlC 1 2+s a ? (hl), then l lC1 *1 l = fh a, @rpa1 1 1 a ? (rpa1) *2 xa, @hl 2 2 xa ? (hl) *1 a, mem 2 2 a ? (mem) *3 xa, mem 2 2 xa ? (mem) *3 a, reg1 1 1 a ? reg1 xa, rp' 2 2 xa ? rp' 50 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area table movt xa, @pcde 1 3 m pd753104 reference xa (pc 11C8 +de) rom m pd753106, 753108 xa (pc 12C8 +de) rom xa, @pcxa 1 3 m pd753104 xa (pc 11C8 +xa) rom m pd753106, 753108 xa (pc 12C8 +xa) rom xa, @bcde 1 3 xa (bcde) rom note *6 xa, @bcxa 1 3 xa (bcxa) rom note *6 bit transfer mov1 cy, fmem.bit 2 2 cy (fmem.bit) *4 cy, pmem.@l 2 2 cy (pmem 7C2 +l 3C2 .bit(l 1C0 )) *5 cy, @h+mem.bit 2 2 cy (h+mem 3C0 .bit) *1 fmem.bit, cy 2 2 (fmem.bit) cy *4 pmem.@l, cy 2 2 (pmem 7C2 +l 3C2 .bit(l 1C0 )) cy *5 @h+mem.bit, cy 2 2 (h+mem 3C0 .bit) cy *1 operation adds a, #n4 1 1+s a a+n4 carry xa, #n8 2 2+s xa xa+n8 carry a, @hl 1 1+s a a+(hl) *1 carry xa, rp' 2 2+s xa xa+rp' carry rp'1, xa 2 2+s rp'1 rp'1+xa carry addc a, @hl 1 1 a, cy a+(hl)+cy *1 xa, rp' 2 2 xa, cy xa+rp'+cy rp'1, xa 2 2 rp'1, cy rp'1+xa+cy subs a, @hl 1 1+s a aC(hl) *1 borrow xa, rp' 2 2+s xa xaCrp' borrow rp'1, xa 2 2+s rp'1 rp'1Cxa borrow subc a, @hl 1 1 a, cy aC(hl)Ccy *1 xa, rp' 2 2 xa, cy xaCrp'Ccy rp'1, xa 2 2 rp'1, cy rp'1CxaCcy note set 0 in b register if the m pd753104 is used. only low-order one bit of b register will be valid if the m pd753106 or 753108 is used. 51 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area operation and a, #n4 2 2 a a ? n4 a, @hl 1 1 a a ? (hl) *1 xa, rp' 2 2 xa xa ? rp' rp'1, xa 2 2 rp'1 rp'1 ? xa or a, #n4 2 2 a a M n4 a, @hl 1 1 a a M (hl) *1 xa, rp' 2 2 xa xa M rp' rp'1, xa 2 2 rp'1 rp'1 M xa xor a, #n4 2 2 a a v n4 a, @hl 1 1 a a v (hl) *1 xa, rp' 2 2 xa xa v rp' rp'1, xa 2 2 rp'1 rp'1 v xa accumulator rorc a 1 1 cy a 0 , a 3 cy, a nC1 a n manipulation not a 2 2 a a increment incs reg 1 1+s reg reg+1 reg = 0 and decrement rp1 1 1+s rp1 rp1+1 rp1 = 00h @hl 2 2+s (hl) (hl)+1 *1 (hl) = 0 mem 2 2+s (mem) (mem)+1 *3 (mem) = 0 decs reg 1 1+s reg regC1 reg = fh rp' 2 2+s rp' rp'C1 rp' = ffh comparison ske reg, #n4 2 2+s skip if reg = n4 reg = n4 @hl, #n4 2 2+s skip if (hl) = n4 *1 (hl) = n4 a, @hl 1 1+s skip if a = (hl) *1 a = (hl) xa, @hl 2 2+s skip if xa = (hl) *1 xa = (hl) a, reg 2 2+s skip if a = reg a = reg xa, rp' 2 2+s skip if xa = rp' xa = rp' carry flag set1 cy 1 1 cy 1 manipulation clr1 cy 1 1 cy 0 skt cy 1 1+s skip if cy = 1 cy = 1 not1 cy 1 1 cy cy 52 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area memory bit set1 mem.bit 2 2 (mem.bit) 1*3 manipulation fmem.bit 2 2 (fmem.bit) 1*4 pmem.@l 2 2 (pmem 7C2 +l 3C2 .bit(l 1C0 )) 1*5 @h+mem.bit 2 2 (h+mem 3C0 .bit) 1*1 clr1 mem.bit 2 2 (mem.bit) 0*3 fmem.bit 2 2 (fmem.bit) 0*4 pmem.@l 2 2 (pmem 7C2 +l 3C2 .bit(l 1C0 )) 0*5 @h+mem.bit 2 2 (h+mem 3C0 .bit) 0*1 skt mem.bit 2 2+s skip if (mem.bit) = 1 *3 (mem.bit) = 1 fmem.bit 2 2+s skip if (fmem.bit) = 1 *4 (fmem.bit) = 1 pmem.@l 2 2+s skip if (pmem 7C2 +l 3C2 .bit(l 1C0 )) = 1 *5 (pmem.@l) = 1 @h+mem.bit 2 2+s skip if (h+mem 3C0 .bit) = 1 *1 (@h+mem.bit) = 1 skf mem.bit 2 2+s skip if (mem.bit) = 0 *3 (mem.bit) = 0 fmem.bit 2 2+s skip if (fmem.bit) = 0 *4 (fmem.bit) = 0 pmem.@l 2 2+s skip if (pmem 7C2 +l 3C2 .bit(l 1C0 )) = 0 *5 (pmem.@l) = 0 @h+mem.bit 2 2+s skip if (h+mem 3C0 .bit) = 0 *1 (@h+mem.bit) = 0 sktclr fmem.bit 2 2+s skip if (fmem.bit) = 1 and clear *4 (fmem.bit) = 1 pmem.@l 2 2+s skip if (pmem 7C2 +l 3C2 .bit(l 1C0 )) = 1 and clear *5 (pmem.@l) = 1 @h+mem.bit 2 2+s skip if (h+mem 3C0 .bit) = 1 and clear *1 (@h+mem.bit) = 1 and1 cy, fmem.bit 2 2 cy cy ? (fmem.bit) *4 cy, pmem.@l 2 2 cy cy ? (pmem 7C2 +l 3C2 .bit(l 1C0 )) *5 cy, @h+mem.bit 2 2 cy cy ? (h+mem 3C0 .bit) *1 or1 cy, fmem.bit 2 2 cy cy M (fmem.bit) *4 cy, pmem.@l 2 2 cy cy M (pmem 7C2 +l 3C2 .bit(l 1C0 )) *5 cy, @h+mem.bit 2 2 cy cy M (h+mem 3C0 .bit) *1 xor1 cy, fmem.bit 2 2 cy cy v (fmem.bit) *4 cy, pmem.@l 2 2 cy cy v (pmem 7C2 +l 3C2 .bit(l 1C0 )) *5 cy, @h+mem.bit 2 2 cy cy v (h+mem 3C0 .bit) *1 53 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area branch br note addr C C m pd753104 *6 pc 11C0 addr select appropriate instruction from among br !addr, brcb !caddr and br $addr according to the assembler being used. m pd753106, 753108 pc 12C0 addr select appropriate instruction from among br !addr, brcb !caddr and br $addr according to the assembler being used. addr1 C C m pd753104 *11 pc 11-0 addr1 select appropriate instruction from among br !addr, bra !addr1, brcb !caddr and br $addr1 according to the assembler being used. m pd753106, 753108 pc 12C0 addr1 select appropriate instruction from among br !addr, bra !addr1, brcb !caddr and br $addr1 according to the assembler being used. !addr 3 3 m pd753104 *6 pc 11C0 addr m pd753106, 753108 pc 12C0 addr $addr 1 2 m pd753104 *7 pc 11C0 addr m pd753106, 753108 pc 12C0 addr $addr1 1 2 m pd753104 pc 11C0 addr1 m pd753106, 753108 pc 12C0 addr1 note the above operations in the double boxes can be performed only in the mk ii mode. the other operations can be performed only in the mk i mode. 54 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area branch br pcde 2 3 m pd753104 pc 11C0 pc 11-8 +de m pd753106, 753108 pc 12C0 pc 12-8 +de pcxa 2 3 m pd753104 pc 11C0 pc 11-8 +xa m pd753106, 753108 pc 12C0 pc 12-8 +xa bcde 2 3 m pd753104 *6 pc 11C0 bcde note 1 m pd753106, 753108 pc 12C0 bcde note 2 bcxa 2 3 m pd753104 *6 pc 11C0 bcxa note 1 m pd753106, 753108 pc 12C0 bcxa note 2 bra note 3 !addr1 3 3 m pd753104 *11 pc 11C0 addr1 m pd753106, 753108 pc 12C0 addr1 brcb !caddr 2 2 m pd753104 *8 pc 11C0 caddr 11C0 m pd753106, 753108 pc 12C0 pc 12 +caddr 11C0 subroutine calla note 3 !addr1 3 3 m pd753104 *11 stack control (spC2) , , mbe, rbe (spC6) (spC3) (spC4) pc 11C0 (spC5) 0, 0, 0, 0 pc 11C0 addr1, sp spC6 m pd753106, 753108 (spC2) , , mbe, rbe (spC6) (spC3) (spC4) pc 11C0 (spC5) 0, 0, 0, pc 12 pc 12C0 addr1, sp spC6 notes 1. 0 must be set to b register. 2. only low-order one bit is valid in b register. 3. the above operations in the double boxes can be performed only in the mk ii mode. the other operations can be performed only in the mk i mode. 55 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area subroutine call note !addr 3 3 m pd753104 *6 stack control (spC3) mbe, rbe, 0, 0 (spC4) (spC1) (spC2) pc 11C0 pc 11C0 addr, sp spC4 m pd753106, 753108 (spC3) mbe, rbe, 0, pc 12 (spC4) (spC1) (spC2) pc 11C0 pc 12C0 addr, sp spC4 4 m pd753104 (spC2) , , mbe, rbe (spC6) (spC3) (spC4) pc 11C0 (spC5) 0, 0, 0, 0 pc 11C0 addr, sp spC6 m pd753106, 753108 (spC2) , , mbe, rbe (spC6) (spC3) (spC4) pc 11C0 (spC5) 0, 0, 0, pc 12 pc 12C0 addr, sp spC6 callf note !faddr 2 2 m pd753104 *9 (spC3) mbe, rbe, 0, 0 (spC4) (spC1) (spC2) pc 11C0 pc 11C0 0+faddr, sp spC4 m pd753106, 753108 (spC3) mbe, rbe, 0, pc 12 (spC4) (spC1) (spC2) pc 11C0 pc 12C0 00+faddr, sp spC4 3 m pd753104 (spC2) , , mbe, rbe (spC6) (spC3) (spC4) pc 11C0 (spC5) 0, 0, 0, 0 pc 11C0 0+faddr, sp spC6 m pd753106, 753108 (spC2) , , mbe, rbe (spC6) (spC3) (spC4) pc 11C0 (spC5) 0, 0, 0, pc 12 pc 12C0 00+faddr, sp spC6 note the above operations in the double boxes can be performed only in the mk ii mode. the other operations can be performed only in the mk i mode. 56 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area subroutine ret note 13 m pd753104 stack control pc 11C0 (sp) (sp+3) (sp+2) mbe, rbe, 0, 0 (sp+1), sp sp+4 m pd753106, 753108 pc 11C0 (sp) (sp+3) (sp+2) mbe, rbe, 0, pc 12 (sp+1), sp sp+4 m pd753104 , , mbe, rbe (sp+4) 0, 0, 0, 0, (sp+1) pc 11C0 (sp) (sp+3) (sp+2), sp sp+6 m pd753106, 753108 , , mbe, rbe (sp+4) mbe, 0, 0, pc 12 (sp+1) pc 11C0 (sp) (sp+3) (sp+2), sp sp+6 rets note 1 3+s m pd753104 unconditional mbe, rbe, 0, 0 (sp+1) pc 11C0 (sp) (sp+3) (sp+2) sp sp+4 then skip unconditionally m pd753106, 753108 mbe, rbe, 0, pc 12 (sp+1) pc 11C0 (sp) (sp+3) (sp+2) sp sp+4 then skip unconditionally m pd753104 0, 0, 0, 0 (sp+1) pc 11C0 (sp) (sp+3) (sp+2) , , mbe, rbe (sp+4) sp sp+6 then skip unconditionally m pd753106, 753108 0, 0, 0, pc 12 (sp+1) pc 11C0 (sp) (sp+3) (sp+2) , , mbe, rbe (sp+4) sp sp+4 then skip unconditionally note the above operations in the double boxes can be performed only in the mk ii mode. the other operations can be performed only in the mk i mode. 57 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area subroutine reti note 1 13 m pd753104 stack control mbe, rbe, 0, 0 (sp+1) pc 11C0 (sp) (sp+3) (sp+2) psw (sp+4) (sp+5), sp sp+6 m pd753106, 753108 mbe, rbe, 0, pc 12 (sp+1) pc 11C0 (sp) (sp+3) (sp+2) psw (sp+4) (sp+5), sp sp+6 m pd753104 0, 0, 0, 0 (sp+1) pc 11C0 (sp) (sp+3) (sp+2) psw (sp+4) (sp+5), sp sp+6 m pd753106, 753108 0, 0, 0, pc 12 (sp+1) pc 11C0 (sp) (sp+3) (sp+2) psw (sp+4) (sp+5), sp sp+6 push rp 1 1 (spC1) (spC2) rp, sp spC2 bs 2 2 (spC1) mbs, (spC2) rbs, sp spC2 pop rp 1 1 rp (sp+1) (sp), sp sp+2 bs 2 2 mbs (sp+1), rbs (sp), sp sp+2 interrupt ei 2 2 ime (ips.3) 1 control ie 22ie 1 di 2 2 ime (ips.3) 0 ie 22ie 0 input/output in note 2 a, portn 2 2 a portn (n = 0 to 3, 5, 6, 8, 9) xa, portn 2 2 xa portn+1, portn (n = 8) out note 2 portn, a 2 2 portn a (n = 3, 5, 6, 8, 9) portn, xa 2 2 portn+1, portn xa (n = 8) cpu control halt 2 2 set halt mode (pcc.2 1) stop 2 2 set stop mode (pcc.3 1) nop 1 1 no operation special sel rbn 2 2 rbs n (n = 0 to 3) mbn 2 2 mbs n (n = 0, 1, 15) notes 1. the above operations in the double boxes can be performed only in the mk ii mode. the other operations can be performed only in the mk i mode. 2. while the in instruction and out instruction are being executed, the mbe must be set to 0 or 1, and mbs must be set to 15. 58 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area special geti note 1, 2 taddr 1 3 m pd753104 *10 ? when tbr instruction pc 11C0 (taddr) 3C0 + (taddr+1) ? when tcall instruction (spC4) (spC1) (spC2) pc 11C0 (spC3) mbe, rbe, 0, 0 pc 11C0 (taddr) 3C0 + (taddr+1) sp spC4 ? when instruction other than tbr and depending on tcall instructions the reference (taddr) (taddr+1) instruction is executed. instruction m pd753106, 753108 ? when tbr instruction pc 12C0 (taddr) 4C0 + (taddr+1) ? when tcall instruction (spC4) (spC1) (spC2) pc 11C0 (spC3) mbe, rbe, 0, pc 12 pc 12C0 (taddr) 4C0 + (taddr+1) sp spC4 ? when instruction other than tbr and depending on tcall instructions the reference (taddr) (taddr+1) instruction is executed. instruction 3 m pd753104 *10 ? when tbr instruction pc 11C0 (taddr) 3C0 + (taddr+1) 4 ? when tcall instruction (spC6) (spC3) (spC4) pc 11C0 (spC5) 0, 0, 0, 0 (spC2) , , mbe, rbe pc 11C0 (taddr) 3C0 + (taddr+1) sp spC6 3 ? when instruction other than tbr and depending on tcall instructions the reference (taddr) (taddr+1) instruction is executed. instruction 3 m pd753106, 753108 ? when tbr instruction pc 12C0 (taddr) 4C0 + (taddr+1) 4 ? when tcall instruction (spC6) (spC3) (spC4) pc 11C0 (spC5) 0, 0, 0, pc 12 (spC2) , , mbe, rbe pc 12C0 (taddr) 4C0 + (taddr+1) sp spC6 3 ? when instruction other than tbr and depending on tcall instructions the reference (taddr) (taddr+1) instruction is executed. instruction notes 1. the tbr and tcall instructions are the table definition assembler pseudo instructions of the geti instruction. 2. the above operations in the double boxes can be performed only in the mk ii mode. the other operations can be performed only in the mk i mode. CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC CCCCCCCCCCCCC CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC CCCCCCCCCCCCC CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC CCCCCCCCCCCCC CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC CCCCCCCCCCCCC CCCCCCCCCCCCC CCCCCCCCCCCCC CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC CCCC CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC CCCC CCCCCCCCCCCCC CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC CCCC CCCCCCCCCCCCC CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC CCCC 59 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 12. electrical specifications absolute maximum ratings (t a = 25?c) parameter symbol test conditions rating unit supply voltage v dd C0.3 to +7.0 v input voltage v i1 except port 5 C0.3 to v dd + 0.3 v v i2 port 5 on-chip pull-up resistor C0.3 to v dd + 0.3 v when n-ch open-drain C0.3 to +14 v output voltage v o C0.3 to v dd + 0.3 v output current, high i oh per pin C10 ma total of all pins C30 ma output current, low i ol per pin 30 ma total of all pins 220 ma operating ambient t a C40 to +85 note ?c temperature storage temperature t stg C65 to +150 ?c note when lcd is driven in normal mode: t a = C10 to +85?c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. capacitance (t a = 25?c, v dd = 0 v) parameter symbol test conditions min. typ. max. unit input capacitance c in f = 1 mhz 15 pf output capacitance c out unmeasured pins returned to 0 v. 15 pf i/o capacitance c io 15 pf 60 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 main system clock oscillator characteristics (t a = C40 to +85?c, v dd = 1.8 to 5.5 v) resonator recommended constant parameter test conditions min. typ. max. unit ceramic oscillation 1.0 6.0 note 2 mhz resonator frequency (fx) note 1 oscillation after v dd reaches oscil- 4 ms stabilization time note 3 lation voltage range min. crystal oscillation 1.0 6.0 note 2 mhz resonator frequency (fx) note 1 oscillation v dd = 4.5 to 5.5 v 10 ms stabilization time note 3 30 external x1 input 1.0 6.0 note 2 mhz clock frequency (fx) note 1 x1 input 83.3 500 ns high/low-level width (t xh , t xl ) notes 1. the oscillation frequency and x1 input frequency indicate only oscillator characteristics. refer to the ac characteristics for instruction execution time. 2. when the oscillation frequency is 4.19 mhz < fx 6.0 mhz at 1.8 v v dd < 2.7 v, setting the processor clock control register (pcc) to 0011 results in 1 machine cycle time being less than the required 0.95 m s. therefore, set pcc to a value other than 0011. 3. the oscillation stabilization time is necessary for oscillation to stabilize after applying v dd or releasing the stop mode. caution when using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with other signal lines. ? do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the oscillator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. x2 x1 c1 c2 v dd x2 x1 c1 c2 v dd x1 x2 61 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 subsystem clock oscillator characteristics (t a = C40 to +85?c, v dd = 1.8 to 5.5 v) resonator recommended constant parameter test conditions min. typ. max. unit crystal oscillation 32 32.768 35 khz resonator frequency (f xt ) note 1 oscillation v dd = 4.5 to 5.5 v 1.0 2 s stabilization time note 2 10 external xt1 input frequency 32 100 khz clock (f xt ) note 1 x1 input high/low-level 5 15 m s width (t xth , t xtl ) notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. the oscillation stabilization time is necessary for oscillation to stabilize after applying v dd . caution when using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with other signal lines. ? do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the oscillator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. the subsystem clock oscillator is designed as a low-amplification circuit for reducing current consumption, and is more prone to malfunction due to noise than the main system clock oscillator. particular care is therefore required with the wiring method when the subsystem clock is used. xt2 xt1 c4 v dd c3 r xt1 xt2 62 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 recommended oscillator constant ceramic resonator (t a = C20 to +85?c) manufacturer product name frequency oscillator oscillation remarks (mhz) constant (pf) voltage range (v dd ) c1 c2 min. max. kyocera kbr-1000f/y 1.0 100 100 1.8 5.5 corporation kbr-2.0ms 2.0 82 82 2.2 kbr-4.19msa 4.19 33 33 1.8 kbr-4.19mks on-chip capacitor product pbrc 4.19a 33 33 pbrc 4.19b on-chip capacitor product kbr-6.0msa 6.0 33 33 kbr-6.0mks on-chip capacitor product pbrc 6.00a 33 33 pbrc 6.00b on-chip capacitor product ceramic resonator (t a = C40 to +85?c) manufacturer product name frequency oscillator oscillation remarks (mhz) constant (pf) voltage range (v dd ) c1 c2 min. max. tdk ccr1000k2 1.0 150 150 2.3 5.5 ccr2.0mc33 2.0 2.0 on-chip capacitor fcr4.19mc5 4.19 product ccr4.19mc3 fcr6.0mc5 6.0 2.2 ccr6.0mc3 caution the oscillator constant and oscillation voltage range indicate conditions of stable oscillation. oscillation frequency precision is not guaranteed. for applications requiring oscillation frequency precision, the oscillation frequency must be adjusted on the implementation circuit. for details, please contact directly the manufacturer of the resonator you will use. 63 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 ceramic resonator (t a = C20 to +80?c) manufacturer product name frequency oscillator oscillation remarks (mhz) constant (pf) voltage range (v dd ) c1 c2 min. max. murata mfg. csb1000j 1.0 100 100 2.4 5.5 rd = 5.6 k w note co., ltd. csa2.00mg 2.0 30 30 1.8 cst2.00mgw on-chip capacitor product csa3.00mg 3.0 30 30 cst3.00mgw on-chip capacitor product csa4.19mg 4.19 30 30 cst4.19mgw on-chip capacitor product csa5.00mg 5.0 30 30 2.2 csa5.00mgu 1.8 cst5.00mgw 2.2 on-chip capacitor product cst5.00mgwu 1.8 csa6.00mg 6.0 30 30 2.5 csa6.00mgu 1.8 cst6.00mgw 2.5 on-chip capacitor product cst6.00mgwu 1.8 note if using the csb1000j (1.0 mhz) ceramic resonator manufactured by murata mfg. co., ltd., a limiting resistor (rd = 5.6 k w ) is required (see figure below). a limiting resistor is not required if using the other recommended resonators. recommended main system clock circuit example (using murata mfg. co., ltd. csb1000j) caution the oscillator constant and oscillation voltage range indicate conditions of stable oscillation. oscillation frequency precision is not guaranteed. for applications requiring oscillation frequency precision, the oscillation frequency must be adjusted on the implementation circuit. for details, please contact directly the manufacturer of the resonator you will use. v dd csb1000j x1 x2 c1 c2 rd 64 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 crystal resonator manufacturer product name frequency oscillator oscillation remarks (mhz) constant (pf) voltage range (v dd ) c1 c2 min. max. kinseki hc-49/u 2.0 15 15 1.8 5.5 t a = C20 to +70 c 4.19 6.0 2.5 5.5 hc-49/u-s 4.19 1.8 5.5 t a = C10 to +70 c 6.0 2.5 5.5 caution the oscillator constant and oscillation voltage range indicate conditions of stable oscillation. oscillation frequency precision is not guaranteed. for applications requiring oscillation frequency precision, the oscillation frequency must be adjusted on the implementation circuit. for details, please contact directly the manufacturer of the resonator you will use. 65 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 dc characteristics (t a = C40 to +85?c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit output current, low i ol per pin 15 ma total of all pins 150 ma input voltage, high v ih1 ports 2, 3, 8, 9 2.7 v dd 5.5 v 0.7v dd v dd v 1.8 v dd < 2.7 v 0.9v dd v dd v v ih2 ports 0, 1, 6, reset 2.7 v dd 5.5 v 0.8v dd v dd v 1.8 v dd < 2.7 v 0.9v dd v dd v v ih3 port 5 on-chip pull-up 2.7 v dd 5.5 v 0.7v dd v dd v resistor 1.8 v dd < 2.7 v 0.9v dd v dd v when n-ch 2.7 v dd 5.5 v 0.7v dd 13 v open-drain 1.8 v dd < 2.7 v 0.9v dd 13 v v ih4 x1, xt1 v dd C0.1 v dd v input voltage, low v il1 ports 2, 3, 5, 8, 9 2.7 v dd 5.5 v 0 0.3v dd v 1.8 v dd < 2.7 v 0 0.1v dd v v il2 ports 0, 1, 6, reset 2.7 v dd 5.5 v 0 0.2v dd v 1.8 v dd < 2.7 v 0 0.1v dd v v il3 x1, xt1 0 0.1 v output voltage, high v oh sck, so, ports 2, 3, 6, 8, 9 i oh = C1.0 ma v dd C0.5 v output voltage, low v ol1 sck, so, ports 2, 3, 5, 6, 8, 9 i ol = 15 ma, 0.2 2.0 v v dd = 4.5 to 5.5 v i ol = 1.6 ma 0.4 v v ol2 sb0, sb1 n-ch open-drain 0.2v dd v pull-up resistor 1 k w input leakage i lih1 v in = v dd pins other than x1, xt1 3 m a current, high i lih2 x1, xt1 20 m a i lih3 v in = 13 v port 5 (when n-ch open-drain) 20 m a input leakage i lil1 v in = 0 v pins other than x1, xt1, port 5 C3 m a current, low i lil2 x1, xt1 C20 m a i lil3 port 5 (when n-ch open-drain) C3 m a when input instruction is not executed port 5 (when n-ch C30 m a open-drain) when input v dd = 5.0 v C10 C27 m a instruction is executed v dd = 3.0 v C3 C8 m a output leakage i loh1 v out = v dd sck, so/sb0, sb1, ports 2, 3, 6, 8, 9, 3 m a current, high port 5 (when n-ch open-drain) i loh2 v out = 13 v port 5 (when n-ch open-drain) 20 m a output leakage i lol v out = 0 v C3 m a current, low on-chip pull-up resistor r l1 v in = 0 v ports 0 to 3, 6, 8, 9 50 100 200 k w (excluding p00 pin) r l2 port 5 (when mask option is selected) 15 30 60 k w 66 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 dc characteristics (t a = C40 to +85?c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit lcd drive voltage v lcd vac0 = 0 ta = C40 to +85 c 2.7 v dd v ta = C10 to +85 c 2.2 v dd v vac0 = 1 1.8 v dd v vac current note 1 i vac vac0 = 1, v dd = 2.0 v 10% 1 4 m a lcd split resistor note 2 r lcd1 50 100 200 k w r lcd2 51020k w lcd output voltage v odc i o = 1.0 m av lcd0 = v lcd 0 0.2 v deviation note 3 (common) v lcd1 = v lcd 2/3 v lcd2 = v lcd 1/3 1.8 v v lcd v dd i o = 5.0 m av lcd0 = v lcd 0 0.2 v v lcd1 = v lcd 2/3 v lcd2 = v lcd 1/3 2.2 v v lcd v dd lcd output voltage v ods i o = 0.5 m av lcd0 = v lcd 0 0.2 v deviation note 3 (segment) v lcd1 = v lcd 2/3 v lcd2 = v lcd 1/3 1.8 v v lcd v dd i o = 1.0 m av lcd0 = v lcd 0 0.2 v v lcd1 = v lcd 2/3 v lcd2 = v lcd 1/3 2.2 v v lcd v dd supply current note 4 i dd1 6.0 mhz note 5 v dd = 5.0 v 10% note 6 1.9 6.0 ma crystal oscillation v dd = 3.0 v 10% note 7 0.4 1.3 ma i dd2 c1 = c2 = 22 pf halt mode v dd = 5.0 v 10% 0.72 2.1 ma v dd = 3.0 v 10% 0.27 0.8 ma i dd1 4.19 mhz note 5 v dd = 5.0 v 10% note 6 1.5 4.0 ma crystal oscillation v dd = 3.0 v 10% note 7 0.25 0.75 ma i dd2 c1 = c2 = 22 pf halt mode v dd = 5.0 v 10% 0.7 2.0 ma v dd = 3.0 v 10% 0.23 0.7 ma i dd3 32.768 khz note 8 low-voltage v dd = 3.0 v 10% 12 35.0 m a crystal oscillation mode note 9 v dd = 2.0 v 10% 4.5 12.0 m a v dd = 3.0 v, t a = 25?c 12 24.0 m a low current consump- v dd = 3.0 v 10% 6.0 18.0 m a tion mode note 10 v dd = 3.0 v, t a = 25?c 6.0 12.0 m a i dd4 halt mode low- v dd = 3.0 v 10% 8.5 25 m a voltage v dd = 2.0 v 10% 3.0 9.0 m a mode note 9 v dd = 3.0 v, t a = 25?c 8.5 17 m a v dd = 3.0 v 10% 3.5 12 m a v dd = 3.0 v, t a = 25?c 3.5 7.0 m a i dd5 xt1 = 0 v note 11 v dd = 5.0 v 10% 0.05 10 m a stop mode v dd = 3.0 v 0.02 5.0 m a 10% t a = 25?c 0.02 3.0 m a low current consumption mode note 10 67 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 notes 1. clear vac0 to 0 in the low current consumption mode and stop mode. when vac0 is set to 1, the current increases by about 1 m a. 2. either r lcd1 or r lcd2 can be selected by the mask option. 3. the voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs (v lcdn ; n = 0, 1, 2). 4. not including currents flowing in on-chip pull-up resistors or lcd split resistors. 5. including oscillation of the subsystem clock. 6. when the processor clock control register (pcc) is set to 0011 and the device is operated in the high- speed mode. 7. when pcc is set to 0000 and the device is operated in the low-speed mode. 8. when the system clock control register (scc) is set to 1001 and the device is operated on the subsystem clock, with main system clock oscillation stopped. 9. when the sub-oscillator control register (sos) is set to 0000. 10. when the sos is set to 0010. 11. when the sos is set to 00 1, and the sub-oscillator feedback resistor is not used ( : dont care). 68 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 1 0 23456 0.5 1 3 2 4 5 6 60 64 supply voltage v dd [v] t cy vs v dd (at main system clock operation) cycle time t cy [ s] operation guaranteed range ac characteristics (t a = C40 to +85?c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit cpu clock cycle t cy operating on v dd = 2.7 to 5.5 v 0.67 64 m s time note 1 main system clock 0.95 64 m s (minimum instruction execution operating on subsystem clock 114 122 125 m s time = 1 machine cycle) ti0, ti1, ti2 input f ti v dd = 2.7 to 5.5 v 0 1.0 mhz frequency 0 275 khz ti0, ti1, ti2 input t tih , t til v dd = 2.7 to 5.5 v 0.48 m s high/low-level width 1.8 m s interrupt input high/ t inth , t intl int0 im02 = 0 note 2 m s low-level width im02 = 1 10 m s int1, 2, 4 10 m s kr0-kr3 10 m s reset low-level width t rsl 10 m s notes 1. the cycle time (minimum instruction execution time) of the cpu clock ( f ) is determined by the oscillation frequency of the connected resonator (and external clock), the system clock control register (scc) and the processor clock control register (pcc). the figure at the right indicates the cycle time t cy versus supply voltage v dd characteristic with the main system clock operating. 2. 2t cy or 128/fx is set by setting the interrupt mode register (im0). 69 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 serial transfer operation 2-wire and 3-wire serial i/o modes (sck...internal clock output): (t a = C40 to +85?c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit sck cycle time t kcy1 v dd = 2.7 to 5.5 v 1300 ns 3800 ns sck high/low-level t kl1 , t kh1 v dd = 2.7 to 5.5 v t kcy1 /2C50 ns width t kcy1 /2C150 ns si note 1 setup time t sik1 v dd = 2.7 to 5.5 v 150 ns (to sck ) 500 ns si note 1 hold time t ksi1 v dd = 2.7 to 5.5 v 400 ns (from sck ) 600 ns delay time from sck ? t kso1 r l = 1 k w , note 2 v dd = 2.7 to 5.5 v 0 250 ns to so note 1 output c l = 100 pf 0 1000 ns notes 1. read as sb0 or sb1 when using the 2-wire serial i/o mode. 2. r l and c l are the load resistance and load capacitance of the so output line. 2-wire and 3-wire serial i/o modes (sck...external clock input): (t a = C40 to +85?c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit sck cycle time t kcy2 v dd = 2.7 to 5.5 v 800 ns 3200 ns sck high/low-level t kl2 , t kh2 v dd = 2.7 to 5.5 v 400 ns width 1600 ns si note 1 setup time t sik2 v dd = 2.7 to 5.5 v 100 ns (to sck ) 150 ns si note 1 hold time t ksi2 v dd = 2.7 to 5.5 v 400 ns (from sck ) 600 ns delay time from sck ? t kso2 r l = 1 k w , note 2 v dd = 2.7 to 5.5 v 0 300 ns to so note 1 output c l = 100 pf 0 1000 ns notes 1. read as sb0 or sb1 when using the 2-wire serial i/o mode. 2. r l and c l are the load resistance and load capacitance of the so output line. 70 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 sbi mode (sck...internal clock output (master)): (t a = C40 to +85?c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit sck cycle time t kcy3 v dd = 2.7 to 5.5 v 1300 ns 3800 ns sck high/low-level t kl3 , t kh3 v dd = 2.7 to 5.5 v t kcy3 /2C50 ns width t kcy3 /2C150 ns sb0, 1 setup time t sik3 v dd = 2.7 to 5.5 v 150 ns (to sck ) 500 ns sb0, 1 hold time (from sck ) t ksi3 t kcy3 /2 ns delay time from sck ? t kso3 r l = 1 k w , note v dd = 2.7 to 5.5 v 0 250 ns to sb0, 1 output c l = 100 pf 0 1000 ns sb0, 1 ? from sck t ksb t kcy3 ns sck ? from sb0, 1 ? t sbk t kcy3 ns sb0, 1 low-level width t sbl t kcy3 ns sb0, 1 high-level width t sbh t kcy3 ns note r l and c l are the load resistance and load capacitance of the sb0, sb1 output line. sbi mode (sck...external clock input (slave)): (t a = C40 to +85?c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit sck cycle time t kcy4 v dd = 2.7 to 5.5 v 800 ns 3200 ns sck high/low-level t kl4 , t kh4 v dd = 2.7 to 5.5 v 400 ns width 1600 ns sb0, 1 setup time t sik4 v dd = 2.7 to 5.5 v 100 ns (to sck ) 150 ns sb0, 1 hold time (from sck ) t ksi4 t kcy4 /2 ns delay time from sck ? t kso4 r l = 1 k w , note v dd = 2.7 to 5.5 v 0 300 ns to sb0, 1 output c l = 100 pf 0 1000 ns sb0, 1 ? from sck t ksb t kcy4 ns sck ? from sb0, 1 ? t sbk t kcy4 ns sb0, 1 low-level width t sbl t kcy4 ns sb0, 1 high-level width t sbh t kcy4 ns note r l and c l are the load resistance and load capacitance of the sb0, sb1 output line. 71 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 ac timing test point (excluding x1, xt1 inputs) clock timing ti0, ti1, ti2 timing v ih (min.) v il (max.) v ih (min.) v il (max.) v oh (min.) v ol (max.) v oh (min.) v ol (max.) ti0, ti1, ti2 1/f ti t til t tih x1 input 1/f x t xl t xh 0.1 v v dd ?.1 v xt1 input 1/f xt t xtl t xth 0.1 v v dd ?.1 v 72 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 serial transfer timing 3-wire serial i/o mode 2-wire serial i/o mode t kso1, 2 t sik1, 2 t kl1, 2 t kh1, 2 sck t ksi1, 2 sb0, 1 t kcy1, 2 t kcy1, 2 t kl1, 2 t kh1, 2 sck si so t sik1, 2 t ksi1, 2 t kso1, 2 input data output data 73 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 serial transfer timing bus release signal transfer command signal transfer interrupt input timing reset input timing t kcy3, 4 t kh3, 4 t ksi3, 4 t sik3, 4 t kso3, 4 sck sb0, 1 t kl3, 4 t sbk t sbh t sbl t ksb t kcy3, 4 t kh3, 4 t ksi3, 4 t sik3, 4 t kso3, 4 sck sb0, 1 t kl3, 4 t sbk t ksb t intl t inth int0, 1, 2, 4 kr0 to 3 t rsl reset 74 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 v dd reset stop instruction execution v dddr stop mode data retention mode internal reset operation halt mode operating mode t srel t wait t srel t wait v dd stop instruction execution v dddr stop mode data retention mode halt mode operating mode standby release signal (interrupt request) data memory stop mode low supply voltage data retention characteristics (t a = C40 to +85?c) parameter symbol test conditions min. typ. max. unit data retention supply voltage v dddr 1.8 5.5 v release signal set time t srel 0 m s oscillation stabilization t wait release by reset note 2 ms wait time note 1 release by interrupt request note 3 ms notes 1. the oscillation stabillization wait time is the time during which the cpu operation is stopped to prevent unstable operation at the oscillation start. 2. either 2 17 /f x or 2 15 /f x can be selected by the mask option. 3. depends on the basic interval timer mode register (btm) settings (see the table below). btm3 btm2 btm1 btm0 wait time fx = at 4.19 mhz fx = at 6.0 mhz 0002 20 /fx (approx. 250 ms) 2 20 /fx (approx. 175 ms) 0112 17 /fx (approx. 31.3 ms) 2 17 /fx (approx. 21.8 ms) 1012 15 /fx (approx. 7.81 ms) 2 15 /fx (approx. 5.46 ms) 1112 13 /fx (approx. 1.95 ms) 2 13 /fx (approx. 1.37 ms) data retention timing (stop mode release by reset) data retention timing (standby release signal: stop mode release by interrupt signal) 75 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 13. characteristic curves (for reference only) i dd vs v dd (main system clock: 6.0 mhz crystal resonator) 10 5.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 012345678 pcc = 0011 pcc = 0010 pcc = 0001 pcc = 0000 xt1 xt2 x1 x2 6.0 mhz 32.768 khz 330 k w 22 pf 22 pf 22 pf 22 pf v dd v dd supply current i dd (ma) main system clock halt mode + 32 khz oscillation subsystem clock operation mode (sos.1 = 0) main system clock stop mode + 32 khz oscillation (sos.1 = 0) subsystem clock halt mode (sos.1 = 0) main system clock stop mode + 32 khz oscillation (sos.1 = 1) and subsystem clock halt mode (sos.1 = 1) crystal resonator crystal resonator supply voltage v dd (v) (t a = 25 c) 76 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 i dd vs v dd (main system clock: 4.19 mhz crystal resonator) 10 5.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 012345678 xt1 xt2 x1 x2 4.19 mhz 32.768 khz 330 k w 22 pf 22 pf 22 pf 22 pf v dd v dd pcc = 0011 pcc = 0010 pcc = 0001 pcc = 0000 main system clock halt mode + 32 khz oscillation subsystem clock operation mode (sos.1 = 0) subsystem clock halt mode (sos.1 = 0) main system clock stop mode + 32 khz oscillation (sos.1 = 0) main system clock stop mode + 32 khz oscillation and subsystem clock halt mode (sos.1 = 1) crystal resonator crystal resonator supply voltage v dd (v) supply current i dd (ma) (t a = 25 c) 77 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 i oh vs v dd v oh (ports 2, 3, 6, 8 and 9) i ol vs v ol (ports 2, 3, 6, 8 and 9) 15 10 5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 v dd = 1.8 v v dd = 2.2 v v dd = 3 v v dd = 4 v v dd = 5.5 v v dd = 5 v v dd v oh [v] (t a = 25?) i oh [ma] 40 30 20 10 0 0 0.5 1.0 1.5 2.0 v dd = 1.8 v v dd = 2.2 v v dd = 3 v v dd = 4 v v dd = 5 v v dd = 5.5 v (t a = 25 c) i ol [ma] v ol [v] 78 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 14. package drawings 48 49 32 64 1 17 16 33 64-pin plastic qfp (14 14) note each lead centerline is located within 0.15 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 17.60.4 14.00.2 0.8 (t.p.) 1.0 j 17.60.4 k p64gc-80-ab8-5 c 14.00.2 i 0.15 1.80.2 l 0.80.2 f 1.0 n p q 0.10 2.550.1 0.10.1 r s 55 2.85 max. h 0.37 +0.08 -0.07 m 0.17 +0.08 -0.07 s s n j detail of lead end c d a b r k m l p i s q g f m h 79 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 64-pin plastic lqfp (12 12) note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 14.80.4 12.00.2 0.13 1.125 i 14.80.4 j c 12.00.2 h 0.320.08 0.65 (t.p.) k 1.40.2 l 0.60.2 f 1.125 p64gk-65-8a8-3 n p q 0.10 1.40.1 0.1250.075 r s 55 1.7 max. m 0.17 +0.08 -0.07 48 49 32 64 1 17 16 33 s s n j detail of lead end c d a b r k m l p i s q g f m h 80 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 48 32 33 64 1 17 16 49 s s 64-pin plastic tqfp (12 12) item millimeters g 1.125 a 14.00.2 c 12.00.2 d f 1.125 14.00.2 b 12.00.2 n 0.10 p q 0.10.05 1.0 s r 3 +4 -3 r h k j q g i s p detail of lead end note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. m h 0.32 +0.06 -0.10 i 0.13 j k 1.00.2 0.65 (t.p.) l 0.5 m 0.17 +0.03 -0.07 p64gk-65-9et-2 t u 0.60.15 0.25 f m a b cd n t l u 1.10.1 81 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 15. recommended soldering conditions the m pd753108 should be soldered and mounted under the conditions recommended in the table below. for details of recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e). for soldering methods and conditions other than those recommended below, contact an nec sales representative. table 15-1. surface mounting type soldering conditions (1/2) (1) m pd753104gc- -ab8 : 64-pin plastic qfp (14 14) m pd753106gc- -ab8 : 64-pin plastic qfp (14 14) m pd753108gc- -ab8 : 64-pin plastic qfp (14 14) soldering soldering conditions symbol method infrared reflow package peak temperature: 235?c, time: 30 seconds max. (at 210?c min.), ir35-00-3 count: three times or less vps package peak temperature: 215?c, time: 40 seconds max. (at 200?c min.), vp15-00-3 count: three times or less wave soldering solder temperature: 260?c max., time: 10 seconds max., count: once, ws60-00-1 preheating temperature: 120?c max. (package surface temperature) partial heating pin temperature: 300?c max., time: 3 seconds max. (per pin row) caution do not use different soldering methods together (except for partial heating). (2) m pd753104gk- -8a8 : 64-pin plastic lqfp (12 12) m pd753106gk- -8a8 : 64-pin plastic lqfp (12 12) m pd753108gk- -8a8 : 64-pin plastic lqfp (12 12) soldering soldering conditions symbol method infrared reflow package peak temperature: 235?c, time: 30 seconds max. (at 210?c min.), ir35-00-2 count: two times or less vps package peak temperature: 215?c, time: 40 seconds max. (at 200?c min.), vp15-00-2 count: two times or less wave soldering solder temperature: 260?c max., time: 10 seconds max., count: once, ws60-00-1 preheating temperature: 120?c max. (package surface temperature) partial heating pin temperature: 300?c max., time: 3 seconds max. (per pin row) caution do not use different soldering methods together (except for partial heating). 82 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 table 15-1. surface mounting type soldering conditions (2/2) (3) m pd753104gk- -9et : 64-pin plastic tqfp (12 12) m pd753106gk- -9et : 64-pin plastic tqfp (12 12) m pd753108gk- -9et : 64-pin plastic tqfp (12 12) soldering soldering conditions symbol method infrared reflow package peak temperature: 235?c, time: 30 seconds max. (at 210?c min.), ir35-107-2 count: two times or less, exposure limit: 7 days note (after that, prebake at 125?c for 10 hours) vps package peak temperature: 215?c, time: 40 seconds max. (at 200?c min.), vp15-107-2 count: two times or less, exposure limit: 7 days note (after that, prebake at 125?c for 10 hours) wave soldering solder bath temperature: 260?c max., time: 10 seconds max., count: once, ws60-107-1 preheating temperature: 120?c max. (package surface temperature), exposure limit: 7 days note (after that, prebake at 125?c for 10 hours) partial heating pin temperature: 300?c max., time: 3 seconds max. (per pin row) note after opening the dry pack, store it at 25?c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating). 83 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 appendix a. m pd75308b, 753108 and 75p3116 functional list parameter m pd75308b m pd753108 m pd75p3116 program memory mask rom mask rom one-time prom 0000h to 1f7fh 0000h to 1fffh 0000h to 3fffh (8064 8 bits) (8192 8 bits) (16384 8 bits) data memory 000h to 1ffh (512 4 bits) cpu 75x standard 75xl cpu instruction when main system clock is 0.95, 1.91, 15.3 m s ? 0.95, 1.91, 3.81, 15.3 m s (during 4.19 mhz operation) execution selected (during 4.19 mhz operation) ? 0.67, 1.33, 2.67, 10.7 m s (during 6.0 mhz operation) time when subsystem clock is 122 m s (32.768 khz operation) selected stack sbs register none sbs.3 = 1: mk i mode selection sbs.3 = 0: mk ii mode selection stack area 000h to 0ffh 000h to 1ffh subroutine call instruction 2-byte stack when mk i mode: 2-byte stack stack operation when mk ii mode: 3-byte stack instruction bra !addr1 unavailable when mk i mode: unavailable calla !addr1 when mk ii mode: available movt xa, @bcde available movt xa, @bcxa br bcde br bcxa call !addr 3 machine cycles mk i mode: 3 machine cycles, mk ii mode: 4 machine cycles callf !faddr 2 machine cycles mk i mode: 2 machine cycles, mk ii mode: 3 machine cycles i/o port cmos input 8 8 cmos input/output 16 20 bit port output 8 0 n-ch open-drain input/output 84 total 40 32 lcd controller/driver segment selection: 24/28/32 segment selection: 16/20/24 segments segments (can be changed to cmos input/output port in 4 time-unit; (can be changed to cmos max. 8) input/output port in 4 time- unit; max. 8) display mode selection: static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias), 1/3 duty (1/3 bias), 1/4 duty (1/3 bias) on-chip split resistor for lcd driver can be specified by using no on-chip split resistor for mask option. lcd driver timer 3 channels 5 channels ? basic interval timer: ? basic interval timer/watchdog timer: 1 channel 1 channel ? 8-bit timer/event counter: 3 channels ? 8-bit timer/event counter: (can be used as 16-bit timer/event counter) 1 channel ? watch timer: 1 channel ? watch timer: 1 channel 84 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 parameter m pd75308b m pd753108 m pd75p3116 clock output (pcl) ? f , 524, 262, 65.5 khz ? f , 524, 262, 65.5 khz (main system clock: (main system clock: during 4.19 mhz operation) during 4.19 mhz operation) ? f , 750, 375, 93.8 khz (main system clock: during 6.0 mhz operation) buz output (buz) ? 2 khz ? 2, 4, 32 khz (main system clock: (main system clock: during 4.19 mhz operation or during 4.19 mhz operation) subsystem clock: during 32.768 khz operation) ? 2.93, 5.86, 46.9 khz (main system clock: 6.0 mhz operation) serial interface 3 modes are available ? 3-wire serial i/o mode ... msb/lsb can be selected for transfer first bit ? 2-wire serial i/o mode ? sbi mode sos feedback resistor cut flag none contained register (sos.0) sub-oscillator current cut flag none contained (sos.1) register bank selection register (rbs) none yes standby release by int0 unavailable available vectored interrupt external: 3, internal: 3 external: 3, internal: 5 supply voltage v dd = 2.0 to 6.0 v v dd = 1.8 to 5.5 v operating ambient temperature t a = C40 to +85?c package ? 80-pin plastic qfp (14 20) ? 64-pin plastic qfp (14 14) ? 64-pin plastic qfp (14 14) ? 80-pin plastic qfp (14 14) ? 64-pin plastic lqfp (12 12) ? 64-pin plastic lqfp (12 12) ? 80-pin plastic tqfp ? 64-pin plastic tqfp (12 12) (fine pitch) (12 12) 85 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 appendix b. development tools the following development tools are provided for system development using the m pd753108. in the 75xl series, the relocatable assembler which is common to the series is used in combination with the device file of each product. language processor ra75x relocatable assembler host machine part number os supply media (product name) pc-9800 series ms-dos? 3.5-inch 2hd m s5a13ra75x ver. 3.30 to ver. 6.2 note ibm pc/at? and refer to 3.5-inch 2hc m s7b13ra75x compatible machines os for ibm pc device file host machine part number os supply media (product name) pc-9800 series ms-dos 3.5-inch 2hd m s5a13df753108 ver. 3.30 to ver. 6.2 note ibm pc/at and refer to 3.5-inch 2hc m s7b13df753108 compatible machines os for ibm pc note ver. 5.00 and later have the task swap function, but it cannot be used for this software. remark operation of the assembler and the device file is guaranteed only on the above host machines and oss. 86 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 prom write tools hardware pg-1500 pg-1500 is a prom programmer which enables you to program single-chip microcontrollers including prom by stand-alone or host machine operation by connecting an attached board and optional programmer adapter to pg-1500. it also enables you to program typical prom devices of 256k bits to 4m bits. pa-75p3116gc prom programmer adapter for the m pd75p3116gc. connect the programmer adapter to pg-1500 for use. pa-75p3116gk prom programmer adapter for the m pd75p3116gk. connect the programmer adapter to pg-1500 for use. software pg-1500 controller pg-1500 and a host machine are connected by serial and parallel interfaces and pg-1500 is controlled on the host machine. host machine part number os supply media (product name) pc-9800 series ms-dos 3.5-inch 2hd m s5a13pg1500 ver. 3.30 to ver. 6.2 note ibm pc/at and refer to 3.5-inch 2hd m s7b13pg1500 compatible machines os for ibm pc note ver. 5.00 and later have the task swap function, but it cannot be used for this software. remark operation of the pg-1500 controller is guaranteed only on the above host machines and oss. 87 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 debugging tool the in-circuit emulators (ie-75000-r and ie-75001-r) are available as the program debugging tool for the m pd753108. the system configurations are described as follows. hardware ie-75000-r note 1 in-circuit emulator for debugging the hardware and software when developing the application systems that use the 75x series and 75xl series. when developing a m pd753108 subseries, the emulation board (ie-75300-r-em) and emulation probe (ep-753108gc-r or ep-753108gk-r) that are sold separately must be used with the ie-75000-r. by connecting with the host machine and the prom programmer, efficient debugging can be made. it contains the emulation board (ie-75000-r-em) which is connected. ie-75001-r in-circuit emulator for debugging the hardware and software when developing the application systems that use the 75x series and 75xl series. when developing a m pd753108 subseries, the emulation board (ie-75300-r-em) and emulation probe (ep-753108gc-r or ep-753108gk-r) that are sold separately must be used with the ie-75001-r. it can debug the system efficiently by connecting the host machine and prom programmer. ie-75300-r-em emulation board for evaluating the application systems that use a m pd753108 subseries. it must be used with the ie-75000-r or ie-75001-r. ep-753108gc-r emulation probe for the m pd753108gc. it must be connected to ie-75000-r (or ie-75001-r) and ie-75300-r-em. it is supplied with the 64-pin conversion socket ev-9200gc-64 which facilitates ev-9200gc-64 connection to a target system. ep-753108gk-r emulation probe for the m pd753108gk. it must be connected to the ie-75000-r (or ie-75001-r) and ie-75300-r-em. it is supplied with the 64-pin conversion adapter tgk-064sbw which facilitates tgk-064sbw note 2 connection to a target system. software ie control program connects the ie-75000-r or ie-75001-r to a host machine via rs-232-c and centronics interface and controls the ie-75000-r or ie-75001-r on a host machine. host machine part no. os supply media (product name) pc-9800 series ms-dos 3.5-inch 2hd m s5a13ie75x ver. 3.30 to 5-inch 2hd m s5a10ie75x ver. 6.2 note 3 ibm pc/at and refer to 3.5-inch 2hc m s7b13ie75x compatible machines os for ibm pc 5-inch 2hc m s7b10ie75x notes 1. maintenance product. 2. this is a product of tokyo eletech corporation. contact: daimaru kogyo, ltd. tokyo electronic department (tel: +81-3-3820-7112) osaka electronic department (tel: +81-6-6244-6672) 3. ver. 5.00 and later have the task swap function, but it cannot be used for this software. remarks 1. operation of the ie control program is guaranteed only on the above host machines and oss. 2. the m pd753104, 753106, 753108 and 75p3116 are commonly referred to as the m pd753108 subseries. 88 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 os for ibm pc the following ibm pc oss are supported. os version pc dos? ver. 3.1 to ver. 6.3 j6.1/v note to j6.3/v note ms-dos ver. 5.0 to ver. 6.22 5.0/v note to 6.2/v note ibm dos? j5.02/v note note only the english mode is supported. caution ver. 5.0 and later have the task swap function, but it cannot be used for this software. 89 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 appendix c. related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. device related documents document name document no. english japanese m pd753104, 753106, 753108 data sheet u10086e (this document) u10086j m pd75p3116 data sheet u11369e u11369j m pd753108 users manual u10890e u10890j 75xl series selection guide u10453e u10453j development tool related documents document name document no. english japanese hardware ie-75000-r/ie-75001-r users manual eeu-1416 eeu-846 ie-75300-r-em users manual u11354e u11354j ep-753108gc/gk-r users manual eeu-1495 eeu-968 pg-1500 users manual u11940e u11940j software ra75x assembler package operation u12622e u12622j users manual language u12385e u12385j pg-1500 controller users manual pc-9800 series eeu-1291 eeu-704 (ms-dos) base ibm pc series u10540e eeu-5008 (pc dos) base other related documents document name document no. english japanese semiconductor selection guide products & packages (cd-rom) x13769x semiconductor device mounting technology manual c10535e c10535j quality grades on nec semiconductor devices c11531e c11531j nec semiconductor device reliability/quality control system c10983e c10983j guide to prevent damage for semiconductor devices by electrostatic c11892e c11892j discharge (esd) guide to microcomputer-related products by third party u11416j caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing. 90 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. 91 m pd753104, 753106, 753108 data sheet u10086ej4v0ds00 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: device availability ordering information product release schedule availability of related technical literature development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. madrid office madrid, spain tel: 91-504-2787 fax: 91-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos-sp brasil tel: 55-11-6462-6810 fax: 55-11-6462-6829 j00.7 m pd753104, 753106, 753108 ms-dos is either a registered trademark or a trademark of microsoft corporation in the united states and/or other countries. ibm dos, pc/at, and pc dos are trademarks of international business machines corporation. m8e 00. 4 the information in this document is current as of september, 2000. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. |
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